Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Skip to main content

Advertisement

Springer Nature Link
Log in

Design of DG FinFET based driver circuits for energy efficient sub threshold global interconnects

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

The proliferation of portable electronics has imposed a pressing need on design of low power circuits. Sub threshold circuits are the ideal candidate to quench the demand of ultra-low power. However, degraded performance and exacerbated variability are the major concerns of sub threshold circuits. Furthermore, the global interconnects significantly affects the performance and power dissipation in sub threshold circuits. The obvious reason is the increased capacitance of long global interconnects which is further augmented with increase in sub threshold CMOS driver resistance. This paper explores the performance of sub threshold global interconnect with six different configurations of DG FinFET driver circuit viz. FinFET SG, TGIG, THYBRID, TGSG, TPIGNSG and TPSGNIG. Performance analysis indicates that FinFET SG configuration exhibits 60.7, 0.8, 2.3, 37 and 40% better energy efficiency compared to TGIG, THYBRID, TGSG, TPIGNSG and TPSGNIG respectively at 225 mV supply voltage. Furthermore, the crosstalk analysis results shows that the glitch amplitude in TGSG driven interconnect and THYBRID driven interconnect is increased by 89.6 and 74% respectively compared to FinFET SG driven interconnect. This work also investigates the suitability of conventional buffer insertion technique for enhancing the performance of DG FinFET driven sub threshold global interconnects. The buffered and un-buffered interconnect shows comparable delay, PDP and EDP in sub threshold region. Furthermore, Monte Carlo analysis results indicate that spread in delay exhibited by FinFET SG driven un-buffered interconnect circuit is lesser by 25% compared to FinFET SG driven buffered circuit in sub threshold region.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20
Fig. 21
Fig. 22
Fig. 23
Fig. 24
Fig. 25
Fig. 26
Fig. 27
Fig. 28
Fig. 29
Fig. 30
Fig. 31
Fig. 32
Fig. 33
Fig. 34
Fig. 35
Fig. 36
Fig. 37
Fig. 38
Fig. 39
Fig. 40
Fig. 41
Fig. 42

Similar content being viewed by others

Data availability

The data supporting the conclusions of this article are included within the article.

References

  1. Reuss, R. H. (2010). Introduction to special issue on circuit technology for ULP. Proceedings of the IEEE, 98(2), 139–143.

    Article  Google Scholar 

  2. Paul, B. C., Agarwal, A., & Roy, K. (2006). Low-power design techniques for scaled technologies. The VLSI Journal, 39, 64–89.

    Article  Google Scholar 

  3. Zhai, B., Blaauw, D., Sylvester, D. and Flautner, D. (2004). Theoretical and practical limits on dynamic voltage scaling. In Design Automation Conf., pp. 868–873.

  4. Calhoun, B., and Chandrakasan, A. (2004). Characterizing and modeling minimum energy operation for subthreshold circuits. In Int. Symp. on Low Power Electronics and Designs, pp. 90–95.

  5. International Technology Roadmap for Semiconductors (ITRS) Reports, 2013 [online]. http://www.itrs.net/reports.html.

  6. Calhoun, B., Ryan, J., Khanna, S., Putic, M., & Lach, J. (2010). Flexible circuits and architechtures for ultralow power. In Proceedings of the IEEE, 98(2), pp. 267–282.

  7. Bakoglu, H. B. (1990). Circuits, interconnects, and packaging for VLSI. Addison-Wesley.

    Google Scholar 

  8. Adler, V., & Friedman, E. G. (1998). Repeater design to reduce delay and power in resistive interconnect. IEEE Transactions on Circuits Systems II, Analog Digital Signal Processing, 45(5), 607–616.

    Article  Google Scholar 

  9. Dave, M., Baghini, M. S., and Sharma, D. (2010). Current mode interconnect. Department Of Electrical Engineering, Indian Institute of Technology, Bombay, 2 December 2010.

  10. Venkatraman, V. and Burleson, W. (2005). Robust multi-level current-mode on-chip interconnect signaling in the presence of process variations. In Sixth international symposium on quality of electronic design.

  11. Kil, J., Gu, J., & Kim, C. H. (2008). A high – speed variation – tolerant interconnect technique for sub-threshold circuits using capacitive boosting. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16(4), 456–465. https://doi.org/10.1145/1165573.1165590

    Article  Google Scholar 

  12. Rahaman, M. S. and Chowdhury, M. H. (2009). Interconnect technique for sub-threshold circuits using negative capacitance effect. In 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, pp. 1122–1125. https://doi.org/10.1109/MWSCAS.2009.5235965.

  13. Pable, S. D., & Hasan, M. (2011). High speed interconnect through device optimization for subthreshold FPGA. Microelectronics Journal, 42(3), 545–552. https://doi.org/10.1016/j.mejo.2010.12.009.

    Article  Google Scholar 

  14. Pable, S. D., & hasan, M. (2012). interconnect design for subthreshold circuits. IEEE Transactions on Nanotechnology, 11(3), 633–639. https://doi.org/10.1109/TNANO.2012.2189015

    Article  Google Scholar 

  15. Singh, A., & Dhiman, R. (2019). Proposal and analysis of mixed CNT bundle for sub-threshold interconnects. IEEE Transactions on Nanotechnology, 18, 584–588. https://doi.org/10.1109/TNANO.2019.2919445

    Article  Google Scholar 

  16. Banerjee, K., & Mehrotra, A. (2002). A power-optimal repeater insertion methodology for global interconnects in nanometer designs. IEEE Transactions on Electron Devices, 49(11), 2001–2007. https://doi.org/10.1109/TED.2002.804706

    Article  Google Scholar 

  17. Jamal, O., & Naeemi, A. (2010). Evolutionary and revolutionary interconnect technologies for performance enhancement of sub-threshold circuits. IEEE International Interconnect Technology Conference. https://doi.org/10.1109/IITC.2010.5510733

    Article  Google Scholar 

  18. Walunj, R. A., Pable, S. D., & Kharate, G. K. (2018). Design considerations and optimisation of clock circuit for ultra-low power sub-threshold applications. Australian Journal of Electrical and Electronics Engineering, 15(3), 98–117. https://doi.org/10.1080/1448837X.2018.1527101

    Article  Google Scholar 

  19. Pable, S. D., & Hasan, M. (2011). Ultra-low-power signaling challenges for subthreshold global interconnects. Integration, The VLSI Journal. https://doi.org/10.1016/j.vlsi.2011.09.001

    Article  Google Scholar 

  20. Nirmal, D., Vijayakumar, P., Samuel, P., Jebalin, B., & Mohankumar, N. (2012). Subthreshold analysis of nanoscaleFinFETs for ultra low power application using high –K dielectric materials. International Journal of Electronics, 100(6), 803–817. https://doi.org/10.1080/00207217.2012.720955

    Article  Google Scholar 

  21. Xiaoxia, W., Feng, W., Yuan, X. (2006). Analysis of SubthresholdFinFET circuits for ultra-low power design. In IEEE International SOC Conference. https://doi.org/10.1109/SOCC.2006.283853.

  22. Walunj, R. A., Pable, S. D., & Kharate, G. K. (2019). Ultra low power DG FinFET based voltage controlled oscillator circuits. International Journal of Electronics, 106(1), 134–159. https://doi.org/10.1080/00207217.2018.1519860

    Article  Google Scholar 

  23. Sharma, V. K., & Pattanaik, M. (2013). VLSI scaling methods and low power CMOS buffer circuits. Journal of Semiconductors. https://doi.org/10.1088/1674-4926/34/9/095001

    Article  Google Scholar 

  24. Weerasekara, R., Pamunuwa, D., Zheng, L., & Tenhunen, H. (2008). Minimal power delay balanced SMART repeaters for global interconnects in the nanometer regime. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16(5), 589–593. https://doi.org/10.1109/TVLSI.2008.917555.

    Article  Google Scholar 

  25. Karthikeyan, A., & Mallick, P. S. (2017). Transmission gate as buffer for carbon-nanotube-based VLSI interconnects. IETE Journal of Research. https://doi.org/10.1080/03772063.2017.1351316

    Article  Google Scholar 

  26. Berkeley Predictive Technology Model, UC Berkeley Device Group. [Online]. Available: /http//www.eas.asu.edu/ptm.

  27. International Technology Roadmap for Semiconductors (ITRS) Reports, (2005) [online]. http://www.itrs.net/reports.html.

  28. Yanambaka, V. P., Mohanty, S. P., Kougianos, E., Ghai, D., & Ghai, G. (2017). Process variation analysis and optimization of a FinFET-based VCO. IEEE Transactions on Semiconductor Manufacturing, 30(2), 126–134. https://doi.org/10.1109/TSM.2017.2669314

    Article  Google Scholar 

  29. Wang, X., Brown, A. R., Cheng, B. and Asenov, A. (2011). Statistical variability and reliability in nanoscale FinFETs. In 2011 International Electron Devices Meeting, pp. 5.4.1–5.4.4. https://doi.org/10.1109/IEDM.2011.6131494.

  30. Rabaey, J. M., Chandrakasan, A. P., & Nikolic, B. (2003). Digital Integrated circuits- a design perspective (2nd ed.). Prentice Hall.

    Google Scholar 

  31. Dhiman, R., & Chandel, R. (2015). Dynamic crosstalk analysis in coupled interconnects for ultra-low power applications. Circuits Syst Signal Process, 34, 21–40. https://doi.org/10.1007/s00034-014-9853-y

    Article  MathSciNet  Google Scholar 

  32. Kaushik, B. K., Sarkar, S., Agarwal, R. P., & Joshi, R. C. (2006). Crosstalk analysis and repeater insertion in crosstalk aware coupled VLSI interconnects. Microelectronics International, 23(3), 55–63. https://doi.org/10.1108/13565360610680776

    Article  Google Scholar 

  33. Farjad, Z., Masoumi, N. (2011). Performance improvement of global interconnects using combined techniques of low swing transceiver and buffer insertion in nano technologies, IEEE, 978–1–4577–2209–7/11.

  34. Khursheed, A., & Khare, K. (2020). Optimized buffer insertion for efficient interconnects designs. In International Journal of Numerical Modelling. pp. e2748, Wiley Publications. https://doi.org/10.1002/jnm.2748.

    Article  Google Scholar 

  35. Bhardwaj, H., Jain, S., & Sohal, H. (2021). Novel global interconnect structure with improved elmore delay estimation for low-power applications. Research Square. https://doi.org/10.21203/rs.3.rs-1031810/v1

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electronics and Telecommunication, Matoshri College of Engineering and Research Centre, Savitribai Phule Pune University, Pune, Maharashtra, India

    R. A. Walunj & G. K. Kharate

Authors
  1. R. A. Walunj
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. G. K. Kharate
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to R. A. Walunj.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Walunj, R.A., Kharate, G.K. Design of DG FinFET based driver circuits for energy efficient sub threshold global interconnects. Analog Integr Circ Sig Process 113, 41–60 (2022). https://doi.org/10.1007/s10470-022-02051-w

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-022-02051-w

Keywords

Search

Navigation