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Analyzing the Impact of Bootstrapped ADC with Augmented NMOS Sleep Transistors Configuration on Performance Parameters

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Abstract

This paper represents an efficient bootstrapped analog to digital converter with augmented NMOS sleep transistors. The newly designed MOS-based bootstrapped circuit is implemented to provide controlled input supply for analog to digital converter to develop the enhancing capability of circuit. This will reduce the effective leakage of the circuit. In the second stage, the NMOS sleep transistors are augmented as pull-up and pull-down transistors. Due to augmentation of transistors, controlled power supply (\(V_{\mathrm{DD}})\) is obtained. Because of this, current driving capability in MOS transistors is improved and minimum sub-threshold leakage current is formed. Due to this, reduction of leakage power dissipation occurs much effectively. The whole simulation has been done at 45 nm (nanometer) technology. It is realized that the leakage power is reduced till 50 % approximately and delay performance is improved. It means that speed is improved using bootstrapped circuit with augmented sleep transistors NMOS. In this paper, different consecutive designs with Analog to Digital converter are represented.

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Acknowledgments

This exertion was supported by ITM University Gwalior in collaboration with Cadence System Design, Bangalore.

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Authors and Affiliations

  1. ITM University, Gwalior, India

    Prateek Jain

  2. ECED, ITM University, Gwalior, India

    Shyam Akashe

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  1. Prateek Jain
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  2. Shyam Akashe
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Correspondence to Prateek Jain.

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Jain, P., Akashe, S. Analyzing the Impact of Bootstrapped ADC with Augmented NMOS Sleep Transistors Configuration on Performance Parameters. Circuits Syst Signal Process 33, 2009–2025 (2014). https://doi.org/10.1007/s00034-013-9736-7

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