Abstract
Sampling switches have a dominant role in switched-capacitor circuits and analog-to-digital convertors. Since they act as input gates, their nonlinearities directly degrade the quality of the input signals. The scaling-down trend of CMOS technology and increasing demands for high-speed and power-efficient circuits pose design challenge in high-speed sampling switches for low-voltage applications. To address this issue, an optimized CMOS switch is proposed in this paper consisting of a bootstrapped NMOS switch and a boosted PMOS switch as a transmission gate. By utilizing this technique, the nonlinearity resulting from the threshold voltage variation (body effect) of NMOS switch is mitigated, considerably. To evaluate the proposed switch, it is designed in 0.18 \(\upmu \hbox {m}\) CMOS process technology. According to the obtained simulation results, this switch can achieve total harmonic distortion of \(-\)78.81 and \(-\)62.99 dB in 100 MS/s at \(V_\mathrm{dd}\) = 1 Volt and 50 MS/s at \(V_\mathrm{dd}\) = 0.8 V, respectively.
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Sarafi, S., Aain, A.K.B. & Abbaszadeh, J. Low-Voltage CMOS Switch for High-Speed Rail-To-Rail Sampling. Circuits Syst Signal Process 35, 771–790 (2016). https://doi.org/10.1007/s00034-015-0101-x
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DOI: https://doi.org/10.1007/s00034-015-0101-x