Abstract
The approximations of fractional-order differentiator/integrator transfer functions are currently performed using integer-order rational functions, which are in general implemented through appropriate multi-feedback topologies. The spreading in the values of time-constants and scaling factors, needed to implement these topologies, increases as the order of the differentiator/integrator and/or the order of the approximation increases. This leads to non-practical values of capacitances and resistances/transconductances in the implementation. A solution to overcome this obstacle is introduced in this paper, based on the employment of a combination of fractional-order and integer-order integrators and differentiators for implementing the desired function. The performance of the proposed scheme is verified through post-layout simulations using Cadence and the Design Kit provided by the Austria Mikro Systeme \(0.35~\upmu \mathrm{m}\) CMOS technology process.
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This article is based upon work from COST Action CA15225, a network supported by COST (European Cooperation in Science and Technology).
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Kapoulea, S., Psychalinos, C. & Elwakil, A.S. Minimization of Spread of Time-Constants and Scaling Factors in Fractional-Order Differentiator and Integrator Realizations. Circuits Syst Signal Process 37, 5647–5663 (2018). https://doi.org/10.1007/s00034-018-0840-6
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DOI: https://doi.org/10.1007/s00034-018-0840-6