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High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core

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Abstract

Emerging high-level hardware description and synthesis technologies in conjunction with field programmable gate arrays (FPGAs) have significantly lowered the threshold for hardware development. Opportunities exist to integrate these technologies into a tool for exploring and evaluating microarchitectural designs especially for newly proposed architectures. This paper presents a prototyping of a new processor core based on Queue architecture as starting point for application-specific processor design exploration. Using a hardware description language, we have created the Synthesizable model of a produced order parallel queue processor core for the integer subset parallel Queue architecture. A prototype implementation is produced by synthesizing the high-level model for the Stratix FPGA prototyping board. We show how to perform prototyping and optimizations to fully exploit the capabilities of the prototyped Queue processor core, while maintaining a common source base.

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Authors and Affiliations

  1. Graduate School of Information Systems, The University of Electro-Communications, 1-5-1 Chofugaoka, Chofu-shi, 182-8585, Tokyo, Japan

    Ben A. Abderazek, Tsutomu Yoshinaga & Masahiro Sowa

Authors
  1. Ben A. Abderazek
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  2. Tsutomu Yoshinaga
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  3. Masahiro Sowa
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Correspondence to Ben A. Abderazek.

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Abderazek, B.A., Yoshinaga, T. & Sowa, M. High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core. J Supercomput 38, 3–15 (2006). https://doi.org/10.1007/s11227-006-6719-5

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  • DOI: https://doi.org/10.1007/s11227-006-6719-5

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