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A localizing directory coherence protocol

Published: 20 June 2004 Publication History
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    User-controllable coherence revives the idea of cooperation between software and hardware in an attempt to bridge the gap between efficient small-scale shared memory machines and massive distributed memory machines. It proposes a new multiprocessor architecture which has both a global address-space and multiple processor-local address-spaces with new memory instructions and a new coherence protocol to manage the dual address-spaces.The purpose of this paper is twofold. First, we solidify the semantics of instruction set extensions that enable "localization" -- the act of moving data from the global address-space to a processor's local address-space -- thus clearly defining the requirements for a localizing coherence protocol. Second, we demonstrate the feasibility of localizing coherence by describing the workings of a full-scale directory-based protocol that we have implemented and tested using an existing protocol specification tool.

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    C. McCurdy and C. Fischer. User-Controllable Coherence for High Performance Shared Memory Multiprocessors. In Proceedings of the Principles and Practice of Parallel Programming (PPoPP), 2003.
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    M. Plakal, D. Sorin, A. Condon, and M. Hill. Lamport Clocks: Verifying a Directory Cache-Coherence Protocol. In Proceedings of the ACM Symposium on Parallel Algorithms and Architectures (SPAA), 1998.
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    D. Culler and J. Singh. Parallel Computer Architecture: A Hardware/Software Approach. Morgan Kaufman, 1999.
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    • (2009)Avoiding cache thrashing due to private data placement in last-level cache for manycore scaling2009 IEEE International Conference on Computer Design10.1109/ICCD.2009.5413143(282-288)Online publication date: Oct-2009

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    cover image ACM Other conferences
    WMPI '04: Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture
    June 2004
    146 pages
    ISBN:159593040X
    DOI:10.1145/1054943
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 20 June 2004

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    Author Tags

    1. distributed memory architectures
    2. irregular computation
    3. parallel computation
    4. shared memory architectures

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    • (2009)Avoiding cache thrashing due to private data placement in last-level cache for manycore scaling2009 IEEE International Conference on Computer Design10.1109/ICCD.2009.5413143(282-288)Online publication date: Oct-2009

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