Article

Implementation of a simple 8-bit microprocessor with reversible energy recovery logic

Authors:

Soo-Ik ChaeAuthors Info & Claims

CF '05: Proceedings of the 2nd conference on Computing frontiers

Pages 421 - 426

https://doi.org/10.1145/1062261.1062332

Published: 04 May 2005 Publication History

Abstract

We describe a simple 8-bit adiabatic microprocessor implemented with nMOS reversible energy recovery logic (nRERL) [1]. The implemented adiabatic microprocessor supports only a subset of the DLX instruction set architecture [15] in order to be fitted into a limited silicon area, and is integrated with an energy-efficient 6-phase clocked power generator (CPG). Phase scheduling was employed to reduce the number of the buffers required in the adiabatic microprocessor. Furthermore, reversibility breaking with self-energy recovery circuits (SERCs) was also employed to reduce energy consumption as well as circuit complexity by. The 8-bit microprocessor core and its on-chip 6-phase CPG were implemented in 0.18-mm CMOS technology. The former and the latter occupied 2.62 x 2.03 mm2 and 1.0 x 0.6 mm2, respectively. From the measurements, we have found that its minimum power consumption is 7.5μW at V_dd =1.8V and f=880kHz

References

[1]

J. Lim, D.-G. Kim, and S.-I Chae, "nMOS reversible energy recovery logic for ultra-low-energy applications," IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp. 865--875, June, 2000.

[2]

C. L. Seitz, A. H. Frey, S. Mattisson, S. D. Rabin, D. A. Speck, and J. L. A. van de Snepscheut, "Hot-clock NMOS," Proc. Chapel Hill Conf. VLSI, 1985, pp.1--17.

[3]

Y. Ye and K. Roy, "QSERL: Quasi-Static Energy Recovery Logic" IEEE Journal of Solid-State Circuits, vol. 36, no. 2, pp. 239--248, Feb. 2001.

[4]

S. Kim and M. C. Papaefthymiou, "True-single-phase adiabatic circuitry," IEEE Transactions on VLSI Systems, vol. 9, issue 1, pp. 52--63, Feb. 2001.

Digital Library

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M. Alioto and G. Palumbo, "NAND/NOR Adiabatic Gates: Power Consumption Evaluation and Comparison Versus the Fan-In" IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 49, No.9, pp. 1253--1262, Sep. 2002.

[6]

W. C. Athas, L. "J." Svensson, J. G. Koller, N. Tzartzanis, and E. Y. Chou, "Low-power digital systems based on adiabatic-switching principles," IEEE Transactions on VLSI Systems., vol. 2, pp. 398--407, Dec. 1994.

Digital Library

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S.G. Younis and T. F. Knight, "Asymptotically zero energy split-level charge recovery logic," Proc. Int. Workshop on Low Power Design, pp. 177--182, April 1994.

[8]

J. Lim, D.-G. Kim, and S.-I Chae, "A 16-b carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems," IEEE Journal of Solid-State Circuits, vol. 34, no. 6, pp. 898--903, June, 1999.

[9]

J. Lim, D.-G. Kim, S.-C. Kang, and S.-I Chae, "An 8x8-b nRERL serial multiplier for ultra-low-power applications," Proc. of ASP-DAC, Jan. 2000, pp 35--36.

Digital Library

[10]

J.-H. Kwon, J. Lim, and S.-I. Chae, "A three-port nRERL register file for utra-low-energy applications," Proc. Int. Symposium on Low-Power Electronics and Design, July 2000, pp.155--160.

Digital Library

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W. C. Athas, N. Tzartzanis, L. "J." Svensson, L. Peterson, H. Li, X. Jiang, and W. -C. Liu, "AC-1: a clock-powered microprocessor," Proc. Int. Symposium on Low-Power Electronics and Design, Aug. 1997, pp. 328--333.

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W. C. Athas, N. Tzartzanis, W. Mao, L. Peterson, R. Lal, K. Chong, J.-S. Moon, L. Svensson and M.Bolotski, "The Design and Implementation of a Low-Power Clock-Powered Microprocessor", IEEE Journal of Solid-State Circuits, vol. 35, no. 11, pp. 1561--1570, Nov. 2000.

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W. C. Athas and L. "J." Svensson, "Reversible logic issues in adiabatic CMOS," Proc. Workshop on Physics and Computing '94, pp. 111--118, Nov. 1994.

[14]

S. Kim and S. -I. Chae, "A simple 8-bit adiabatic microprocessor that consumed 7.8mW at 880kHz," under preparation

[15]

J. L. Hennessy and D. A. Patterson, "Computer Architecture," Morgan Kaufmann Publishers Inc. 1990

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Cited By

Ayala CTanaka TSaito RNozoe MTakeuchi NYoshikawa N(2021)MANA: A Monolithic Adiabatic iNtegration Architecture Microprocessor Using 1.4-zJ/op Unshunted Superconductor Josephson Junction DevicesIEEE Journal of Solid-State Circuits10.1109/JSSC.2020.304133856:4(1152-1165)Online publication date: Apr-2021
https://doi.org/10.1109/JSSC.2020.3041338
Nayeem NRice J(2013)Online Testable Approaches in Reversible LogicJournal of Electronic Testing: Theory and Applications10.1007/s10836-013-5399-329:6(763-778)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1007/s10836-013-5399-3
Kim SChae SRoy KTiwari V(2005)Complexity reduction in an nRERL microprocessorProceedings of the 2005 international symposium on Low power electronics and design10.1145/1077603.1077649(180-185)Online publication date: 8-Aug-2005
https://dl.acm.org/doi/10.1145/1077603.1077649
Show More Cited By

Index Terms

Implementation of a simple 8-bit microprocessor with reversible energy recovery logic
1. Hardware
  1. Integrated circuits

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cover image ACM Conferences

CF '05: Proceedings of the 2nd conference on Computing frontiers

May 2005

467 pages

ISBN:1595930191

DOI:10.1145/1062261

General Chair:
Nader Bagherzadeh,
Program Chairs:
Mateo Valero,
Alex Ramirez

Copyright © 2005 ACM.

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Published: 04 May 2005

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Cited By

Ayala CTanaka TSaito RNozoe MTakeuchi NYoshikawa N(2021)MANA: A Monolithic Adiabatic iNtegration Architecture Microprocessor Using 1.4-zJ/op Unshunted Superconductor Josephson Junction DevicesIEEE Journal of Solid-State Circuits10.1109/JSSC.2020.304133856:4(1152-1165)Online publication date: Apr-2021
https://doi.org/10.1109/JSSC.2020.3041338
Nayeem NRice J(2013)Online Testable Approaches in Reversible LogicJournal of Electronic Testing: Theory and Applications10.1007/s10836-013-5399-329:6(763-778)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1007/s10836-013-5399-3
Kim SChae SRoy KTiwari V(2005)Complexity reduction in an nRERL microprocessorProceedings of the 2005 international symposium on Low power electronics and design10.1145/1077603.1077649(180-185)Online publication date: 8-Aug-2005
https://dl.acm.org/doi/10.1145/1077603.1077649
Seokkee Kim Soo-lk Chae (2005)Complexity reduction in an nRERL microprocessorISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.10.1109/LPE.2005.195511(180-185)Online publication date: 2005
https://doi.org/10.1109/LPE.2005.195511

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