Article

Race-condition-aware clock skew scheduling

Authors:

Shih-Hsu Huang,

Yow-Tyng Nieh,

Feng-Pin LuAuthors Info & Claims

DAC '05: Proceedings of the 42nd annual Design Automation Conference

Pages 475 - 478

https://doi.org/10.1145/1065579.1065704

Published: 13 June 2005 Publication History

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Abstract

The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and delay insertion (for resolving the race conditions) may lead to further clock period reduction. However, the interactions between clock skew scheduling and delay insertion have not been well studied. In this paper, we provide a fresh viewpoint to look at this problem. A novel approach, called race-condition-aware (RCA) clock skew scheduling, is proposed to determine the clock skew schedule by taking the race conditions into account. Our objective is not only to optimize the clock period, but also to heuristically minimize the required inserted delay. Compared with previous work, our approach has significant improvement in the time complexity.

References

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J.P. Fishburn, "Clock Skew Optimization", IEEE Trans. on Computers, Vol. 39, No. 7, pp. 945--951, 1990.

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[2]

R.B. Deokar and S.S. Sapatnekar, "A Graph-Theoretic Approach to Clock Skew Optimization", Proc. of IEEE International Symposium on Circuits and Systems, Vol. 1, pp.407--410, 1994.

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M.C. Papaefthymiou, "Understanding Retiming through Maximum Average-Delay Cycles", Mathematical Systems Theory, Vol. 27, pp. 65--84, 1994.

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N.V. Shenoy, R.K. Brayton and A.L. Sangiovanni-Vincentelli, "Minimum Padding to Satisfy Short Path Constraints", Proc. of IEEE/ACM International Conference on Computer Aided Design, pp. 156--161, 1993.

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[5]

S.H. Huang and Y.T. Nieh, "Clock Period Minimization of Non-Zero Clock Skew Circuits", Proc. of IEEE/ACM International Conference on Computer Aided Design, pp. 809--812, 2003.

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Cited By

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Zhou XLuk WZhou HYang FYan CZeng X(2015)Multi-parameter clock skew schedulingIntegration, the VLSI Journal10.1016/j.vlsi.2014.07.00548:C(129-137)Online publication date: 1-Jan-2015
https://dl.acm.org/doi/10.1016/j.vlsi.2014.07.005
Tu WHuang SCheng CMacii E(2013)Co-synthesis of data paths and clock control paths for minimum-period clock gatingProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485720(1831-1836)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485720
ZHI YLUK WWANG YYAN CZENG X(2012)Yield-Driven Clock Skew Scheduling for Arbitrary Distributions of Critical Path DelaysIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E95.A.2172E95.A:12(2172-2181)Online publication date: 2012
https://doi.org/10.1587/transfun.E95.A.2172
Show More Cited By

Index Terms

Race-condition-aware clock skew scheduling
1. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization

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Information & Contributors

Information

Published In

DAC '05: Proceedings of the 42nd annual Design Automation Conference

June 2005

984 pages

ISBN:1595930582

DOI:10.1145/1065579

General Chair:
William H. Joyner
IBM Corp./SRC
,
Program Chairs:
Grant E. Martin
Tensilica, Inc.
,
Andrew B. Kahng
University of California at San Diego, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2005

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DAC05: The 42nd Annual Design Automation Conference 2005

June 13 - 17, 2005

California, Anaheim, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Zhou XLuk WZhou HYang FYan CZeng X(2015)Multi-parameter clock skew schedulingIntegration, the VLSI Journal10.1016/j.vlsi.2014.07.00548:C(129-137)Online publication date: 1-Jan-2015
https://dl.acm.org/doi/10.1016/j.vlsi.2014.07.005
Tu WHuang SCheng CMacii E(2013)Co-synthesis of data paths and clock control paths for minimum-period clock gatingProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485720(1831-1836)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485720
ZHI YLUK WWANG YYAN CZENG X(2012)Yield-Driven Clock Skew Scheduling for Arbitrary Distributions of Critical Path DelaysIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E95.A.2172E95.A:12(2172-2181)Online publication date: 2012
https://doi.org/10.1587/transfun.E95.A.2172
Huang SJhuo GHuang W(2010)Minimum buffer insertions for clock period minimization2010 International Symposium on Computer, Communication, Control and Automation (3CA)10.1109/3CA.2010.5533776(426-429)Online publication date: May-2010
https://doi.org/10.1109/3CA.2010.5533776
Dong XLemieux G(2009)PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess2009 International Conference on Field-Programmable Technology10.1109/FPT.2009.5377666(88-95)Online publication date: Dec-2009
https://doi.org/10.1109/FPT.2009.5377666
Wang YLuk WZeng XTao JYan CTong JCai WNi JFix L(2008)Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delaysProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391525(223-226)Online publication date: 8-Jun-2008
https://dl.acm.org/doi/10.1145/1391469.1391525
Huang SCheng CChang CNieh YLevitan S(2007)Clock period minimization with minimum delay insertionProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278720(970-975)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278720

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Clock skew scheduling with race conditions considered

Clock period minimization with minimum delay insertion

Delay insertion method in clock skew scheduling