Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper we report on the verification of a Very Large Instruction Word processor. The verification team used a sophisticated test program generator that modeled the parallel aspects as sequential constraints, and augmented the tool with manually written test templates. The system created large numbers of legal stimuli, however the quality of the tests was proved insufficient by several post silicon bugs. We analyze this experience and suggest an alternative, parallel generation technique. We show through experiments the feasibility of the new technique and its superior quality along several dimensions. We claim that the results apply to other parallel architectures and verification environments.

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Cited By

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Rich KShaw RGovindaraju SDobrikin D(2006)DVGen: Increasing Coverage by Automatically Combining Test Specifications2006 IEEE International High Level Design Validation and Test Workshop10.1109/HLDVT.2006.320011(3-10)Online publication date: Nov-2006
https://doi.org/10.1109/HLDVT.2006.320011

Index Terms

VLIW: a case study of parallelism verification
1. Hardware
  1. Hardware validation
    1. Functional verification

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DAC '05: Proceedings of the 42nd annual Design Automation Conference

June 2005

984 pages

ISBN:1595930582

DOI:10.1145/1065579

General Chair:
William H. Joyner
IBM Corp./SRC
,
Program Chairs:
Grant E. Martin
Tensilica, Inc.
,
Andrew B. Kahng
University of California at San Diego, CA

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Published: 13 June 2005

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Rich KShaw RGovindaraju SDobrikin D(2006)DVGen: Increasing Coverage by Automatically Combining Test Specifications2006 IEEE International High Level Design Validation and Test Workshop10.1109/HLDVT.2006.320011(3-10)Online publication date: Nov-2006
https://doi.org/10.1109/HLDVT.2006.320011

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Dynamically Scheduling VLIW Instructions

Advances in simultaneous multithreading testcase generation methods

EPEX: Processor Verification by Equivalent Program Execution