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High-bandwidth data memory systems for superscalar processors

Authors:

Gurindar S. Sohi,

Manoj FranklinAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 19, Issue 2

Pages 53 - 62

https://doi.org/10.1145/106975.106980

Published: 01 April 1991 Publication History

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References

[1]

H.O. Bugge, E. H. Kristiansen, and B. O. Bakka, "Trace-Driven Simulations for a Two-Level Cache Design in Open Bus Systems," in Proc. 17th Annual Symposium on Computer Architecture, Seattle, WA, pp. 250-259, May 1990.

Digital Library

Google Scholar

[2]

P.P. Gelsinger, P. A. Gargini, G. H. Parker, and A. Y. C. Yu, "Microprocessors circa 2000," IEEE Spectrum, vol. 26, pp. 43-47, October 1989.

Digital Library

Google Scholar

[3]

J.R. Goodman, "Using Cache Memory to Reduce Processor-Memory Traffic," Proc. l Oth Annual Symposium on Computer Architecture, pp. 124- 131, June 1983.

Digital Library

Google Scholar

[4]

G.F. Grohoski, "Machine Organization of the IBM RISC System/6000 processor," IBM Journal of Research and Development, vol. 34, pp. 37-58, January 1990.

Digital Library

Google Scholar

[5]

P.Y.T. Hsu and E. S. Davidson, "Highly Concurrent Scalar Processing," Proc. 13th Annual Symposium on Computer Architecture, pp. 386- 395, June 1986.

Digital Library

Google Scholar

[6]

N.P. Jouppi and D. W. Wall, "Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines," in Proc. ASPLOS iii, Boston, MA, pp. 272-282, April 1989.

Digital Library

Google Scholar

[7]

N.P. Jouppi, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully- Associative Cache and Prefetch Buffers," in Proc. 17th Annual Symposium on Computer Architecture, Seattle, WA, pp. 364-373, May 1990.

Digital Library

Google Scholar

[8]

D. Kroft, "Lockup-Free Instruction Fetch/Prefetch Cache Organization," Proc. 8th International Symposium on Computer Architecture, pp. 81-87, May 1981.

Digital Library

Google Scholar

[9]

S.W. Melvin, M. C. Shebanow, and Y. N. Patt, "Hardware Supixnt for Large Atomic Units in Dynamically Scheduled Machines," in Proc. 21st Annual Workshop on Microprogramming and Microarchitecture, San Diego, CA, November 1988.

Digital Library

Google Scholar

[10]

K. Murakami, N. Irie, M. Kuga, and S. Tomita, "SIMP (Single Instruction Stream /Multiple Instruction Pipelining): A Novel High-Speed Single- Processor Architecture," in Proc. 16th Annual Symposium on Computer Architecture, jerusalem, Israel, pp. 78-85, May 1989.

Digital Library

Google Scholar

[11]

Y.N. Patlg W. W. Hwu, and M. Shebanow, "HPS, A New Microarchitecture: Rationale and Introduction,'' in Proc. 18th Annual Workshop on Microprogramming, Pacific Grove, CA, pp. 103-108, December 1985.

Digital Library

Google Scholar

[12]

D.N. Pnevmatikatos and M. D. Hill, "Cache Performance of the Integer SPEC Benchmarks on a RISC," ACM SIGARCH Computer Architecture News, vol. 18, pp. 53-68, June 1990.

Digital Library

Google Scholar

[13]

S.A. Przybylski, Cache and Memory Hierarchy Design: A Performance Directed Approach. San Mateo, California: Morgan Kaufmann, 1990.

Digital Library

Google Scholar

[14]

B.R. Rau, M. S Schlansker, and D. W. L. Yen, "The CydraTM 5 Stride-Insensitive Memory System,'' in 1989 Int. Conference on Parallel Processing, St. Charles, IL, August 1989.

Google Scholar

[15]

A.J. Smith, "Cache Memories," ACM Computing Surveys, vol. 14, pp. 473-530, September 1982.

Digital Library

Google Scholar

[16]

A.J. Smith, "Bibliography and Readings on CPU Cache Memories and Related Topics," ACM SiGARCH Computer Architecture News, vol. 14, pp. 22-42, January 1986.

Digital Library

Google Scholar

[17]

J.E. Smith, "Decoupled Access/Execute Architectures,'' Proc. 9th Annual Symposium on Computer Architecture, pp. 112-119, April 1982.

Digital Library

Google Scholar

[18]

M.D. Smith, M. S. Lam, and M. A. Horowitz, "Boosting Beyond Static Scheduling in a Superscalar Processor," in Proc. 17th Annual Symposium on Computer Architecture, Seattle, WA, pp. 344-354, May 1990.

Digital Library

Google Scholar

[19]

G. S. Sohi, "High-Bandwidth Interleaved Memories for Vector Processors - A Simulation Study," Computer Sciences Technical Report //790, University of Wisconsin-Madison, Madison, WI 53706, September 1988.

Google Scholar

[20]

G.S. Sohi, "Instruction Issue Logic for High- Performance, Interruptible, Multiple Functional Unit, Pipelined Computers," IEEE Trans. on Computers, vol. 39, pp. 349-359, March 1990.

Digital Library

Google Scholar

Cited By

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Kim YKim HSong W(2023)NOMAD: Enabling Non-blocking OS-managed DRAM Cache via Tag-Data Decoupling2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071016(193-205)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10071016
Richardson JGeorge ACheng KLam H(2016)Analysis of Fixed, Reconfigurable, and Hybrid Devices with Computational, Memory, I/O, & Realizable-Utilization MetricsACM Transactions on Reconfigurable Technology and Systems10.1145/288840110:1(1-21)Online publication date: 24-Sep-2016
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Williams JMassie CGeorge ARichardson JGosrani KLam H(2010)Characterization of Fixed and Reconfigurable Multi-Core Devices for Application AccelerationACM Transactions on Reconfigurable Technology and Systems10.1145/1862648.18626493:4(1-29)Online publication date: 1-Nov-2010
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Index Terms

High-bandwidth data memory systems for superscalar processors
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Modeling methodologies
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory
  2. Very large scale integration design

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cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 19, Issue 2

Apr. 1991

305 pages

ISSN:0163-5964

DOI:10.1145/106975

Editor:
David A. Patterson
Univ. of California, Berkeley

Issue’s Table of Contents

ASPLOS IV: Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
April 1991
320 pages
ISBN:0897913809
DOI:10.1145/106972
Chairman:
David A. Patterson
Univ. of California, Berkeley
,
General Chair:
Bob Rau

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 April 1991

Published in SIGARCH Volume 19, Issue 2

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Kim YKim HSong W(2023)NOMAD: Enabling Non-blocking OS-managed DRAM Cache via Tag-Data Decoupling2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071016(193-205)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10071016
Richardson JGeorge ACheng KLam H(2016)Analysis of Fixed, Reconfigurable, and Hybrid Devices with Computational, Memory, I/O, & Realizable-Utilization MetricsACM Transactions on Reconfigurable Technology and Systems10.1145/288840110:1(1-21)Online publication date: 24-Sep-2016
https://dl.acm.org/doi/10.1145/2888401
Williams JMassie CGeorge ARichardson JGosrani KLam H(2010)Characterization of Fixed and Reconfigurable Multi-Core Devices for Application AccelerationACM Transactions on Reconfigurable Technology and Systems10.1145/1862648.18626493:4(1-29)Online publication date: 1-Nov-2010
https://dl.acm.org/doi/10.1145/1862648.1862649
Kim YKim HSong W(2023)NOMAD: Enabling Non-blocking OS-managed DRAM Cache via Tag-Data Decoupling2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071016(193-205)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10071016
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Complexity-effective superscalar processors

A low-complexity fetch architecture for high-performance superscalar processors

Single FU bypass networks for high clock rate superscalar processors

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