A low-power, multichannel gated oscillator-based CDR for short-haul applications
Pages 107 - 110
Abstract
A gated current-controlled oscillator (GCCO) based topology is used to implement a low-power multi-channel clock and data recovery (CDR) system in a 0.18um digital CMOS technology. A systematic approach is presented to design a reliable and low-power system based on the required specifications. Behavioral simulations are also used to estimate the achievable bit error rate (BER), jitter tolerance (JTOL), and frequency offset tolerance (FTOL) of the proposed CDR. Using a single 1.8V supply voltage, the proposed 20Gbps 8-channel CDR consumes only 70.2mW or 3.51mW/Channel/Gbps while occupies 0.045mm2 silicon area
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Publication History
Published: 08 August 2005
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ISLPED05: International Symposium on Low Power Electronics and Design
August 8 - 10, 2005
CA, San Diego, USA
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