Article

FlexPath NP: a network processor concept with application-driven flexible processing paths

Authors:

Rainer Ohlendorf,

Andreas Herkersdorf,

Thomas WildAuthors Info & Claims

CODES+ISSS '05: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Pages 279 - 284

https://doi.org/10.1145/1084834.1084904

Published: 19 September 2005 Publication History

Abstract

In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP) application sub-functions onto both SW programmable processor (CPU) resources and (re-)configurable HW building blocks, such that different packet flows are forwarded via different, optimized processing paths through the NP. Packets with well understood, relatively simple processing requirements may even bypass the central CPU complex (AutoRoute). In consequence, CPU processing resources are more effectively used and the overall NP performance and throughput are improved compared to conventional NP architectures. We present analytical performance estimations to quantify the performance advantage of FlexPath (expressed as available CPU instructions for each packet traversing the CPUs) and introduce a platform-based System on Programmable Chip (SoPC) based architecture which implements the FlexPath NP concept.

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Cited By

Salehi MFakhraie SYazdanbakhsh A(2012)Instruction set architectural guidelines for embedded packet-processing enginesJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2012.02.00458:3-4(112-125)Online publication date: 1-Mar-2012
https://dl.acm.org/doi/10.1016/j.sysarc.2012.02.004
Leu FJenq FJiang F(2011)A path switching scheme for SCTP based on round trip delaysComputers & Mathematics with Applications10.1016/j.camwa.2011.08.06662:9(3504-3523)Online publication date: 1-Nov-2011
https://dl.acm.org/doi/10.1016/j.camwa.2011.08.066
Ohlendorf RMeitinger MWild THerkersdorf A(2010)FlexPath NP—Flexible, Dynamically Reconfigurable Processing Paths in Network ProcessorsDynamically Reconfigurable Systems10.1007/978-90-481-3485-4_17(355-374)Online publication date: 10-Feb-2010
https://doi.org/10.1007/978-90-481-3485-4_17
Show More Cited By

Index Terms

FlexPath NP: a network processor concept with application-driven flexible processing paths
1. Computer systems organization
  1. Architectures
    1. Other architectures
    2. Serial architectures
      1. Pipeline computing
2. Networks
  1. Network components
    1. Intermediate nodes
      1. Routers

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Published In

cover image ACM Conferences

CODES+ISSS '05: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

September 2005

356 pages

ISBN:1595931619

DOI:10.1145/1084834

General Chairs:
Petru Eles
Linköping University, Sweden
,
Axel Jantsch
Royal Institute of Technology, Sweden
,
Program Chair:
Reinaldo Bergamaschi
IBM T. J. Watson Research Center

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 19 September 2005

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CODES/ISSS05

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CODES/ISSS05: Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

September 19 - 21, 2005

NJ, Jersey City, USA

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CODES+ISSS '05 Paper Acceptance Rate 50 of 200 submissions, 25%;

Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

Salehi MFakhraie SYazdanbakhsh A(2012)Instruction set architectural guidelines for embedded packet-processing enginesJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2012.02.00458:3-4(112-125)Online publication date: 1-Mar-2012
https://dl.acm.org/doi/10.1016/j.sysarc.2012.02.004
Leu FJenq FJiang F(2011)A path switching scheme for SCTP based on round trip delaysComputers & Mathematics with Applications10.1016/j.camwa.2011.08.06662:9(3504-3523)Online publication date: 1-Nov-2011
https://dl.acm.org/doi/10.1016/j.camwa.2011.08.066
Ohlendorf RMeitinger MWild THerkersdorf A(2010)FlexPath NP—Flexible, Dynamically Reconfigurable Processing Paths in Network ProcessorsDynamically Reconfigurable Systems10.1007/978-90-481-3485-4_17(355-374)Online publication date: 10-Feb-2010
https://doi.org/10.1007/978-90-481-3485-4_17
Herkersdorf ALankes AMeitinger MOhlendorf RWallentowitz SWild TZeppenfeld J(2010)Hardware Support for Efficient Resource Utilization in Manycore Processor SystemsMultiprocessor System-on-Chip10.1007/978-1-4419-6460-1_3(57-87)Online publication date: 9-Nov-2010
https://doi.org/10.1007/978-1-4419-6460-1_3
Salehi MFakhraie S(2009)Quantitative analysis of packet-processing applications regarding architectural guidelines for network-processing-engine developmentJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2009.07.00155:7-9(373-386)Online publication date: 1-Jul-2009
https://dl.acm.org/doi/10.1016/j.sysarc.2009.07.001
Meitinger MOhlendorf RWild THerkersdorf A(2008)A hardware packet re-sequencer unit for network processorsProceedings of the 21st international conference on Architecture of computing systems10.5555/1787770.1787782(85-97)Online publication date: 25-Feb-2008
https://dl.acm.org/doi/10.5555/1787770.1787782
Ohlendorf RMeitinger MWild THerkersdorf A(2008)A processing path dispatcher in network processor MPSoCsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200204816:10(1335-1345)Online publication date: 1-Oct-2008
https://dl.acm.org/doi/10.1109/TVLSI.2008.2002048
Meitinger MOhlendorf RWild THerkersdorf A(2008)A Hardware Packet Re-Sequencer Unit for Network ProcessorsArchitecture of Computing Systems – ARCS 200810.1007/978-3-540-78153-0_8(85-97)Online publication date: 2008
https://doi.org/10.1007/978-3-540-78153-0_8
Ohlendorf RWild TMeitinger MRauchfuss HHerkersdorf A(2007)Simulated and measured performance evaluation of RISC-based SoC platforms in network processing applicationsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2007.01.00953:10(703-718)Online publication date: 1-Oct-2007
https://dl.acm.org/doi/10.1016/j.sysarc.2007.01.009
Wild THerkersdorf AOhlendorf RGielen G(2006)Performance evaluation for system-on-chip architectures using trace-based transaction level simulationProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131549(248-253)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131549
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