Efficient embedded software design with synchronous models

Reviewer: Suyash Sinha

An inter-task communication mechanism for improving the efficiency of model-based software designs by relaxing some unnecessary computational constraints imposed by synchronous assumption is proposed in this paper. In particular, the proposal is a generalization of an inter-task communication mechanism explored earlier by Scaife and Caspi [1]. The efficiency gain essentially comes from deferring certain block computations as long as the deadlines for system timing specification are met. To model this de-synchronization, the authors make use of tagging functions for signals and triggering events. As such, the authors contend that the synchronous model can be correctly implemented by implementing buffers on signals, tagging functions, and ensuring producer-consumer precedence constraints. The authors derive formulae for sizing the communication buffers. Then, they discuss implementations for uniprocessor, multiprocessor, and distributed systems. The single processor implementation uses a shared circular buffer with producer and consumer write and read pointers updated by tagging functions at producer and consumer ends, with the caveat that all tagging operations must execute atomically. When the producer and consumers are scheduled on different processors, a locking mechanism needs to be used, which, in turn, could lead to execution order violation. The authors discuss a way to avoid such inversion. Distributed systems have yet another issue of synchronizing clocks across nodes, which is discussed in the paper. The authors could have included more detail about practical efficiency gains using this method by providing a real application example. It might be especially interesting in cases of multiprocessor and distributed system implementations, where lock contentions and clock synchronization protocols might cause significant overheads. Perhaps these issues will be discussed in a future paper. Online Computing Reviews Service