Article

A heterogeneously segmented cache architecture for a packet forwarding engine

Authors:

R. GovindarajanAuthors Info & Claims

ICS '05: Proceedings of the 19th annual international conference on Supercomputing

Pages 71 - 80

https://doi.org/10.1145/1088149.1088159

Published: 20 June 2005 Publication History

Abstract

As network traffic continues to increase and with the requirement to process packets at line rates, high performance routers need to forward millions of packets every second. Even with an efficient lookup algorithm like the LC-trie, each packet needs upto 5 memory accesses. Earlier work shows that a single cache for the nodes of an LC-trie can reduce the number of external memory accesses.We observe that the locality characteristics of the level-one nodes of an LC-trie are significantly different from those of lower-level nodes. Hence, we propose a heterogeneously segmented cache architecture (HSCA) which uses separate caches for level-one and lower-level nodes each with carefully chosen sizes. We further improve the hit rate of the level-one nodes cache by introducing a weight-based replacement policy and an intelligent index bit selection scheme. To evaluate our cache scheme with realistic traces, we propose a synthetic trace generation method which emulates real traces and can generate traces with varying locality characteristics. The base HSCA scheme gives us upto 16% reduction in misses over the unified scheme. The optimizations further enhance this improvement to upto 25% for core router traces.

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Cited By

Rajan KGovindarajan R(2009)A Novel Cache Architecture and Placement Framework for Packet Forwarding EnginesIEEE Transactions on Computers10.1109/TC.2009.1858:8(1009-1025)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1109/TC.2009.18
Liu ZYu JWang XLiu BBhuyan L(2008)Revisiting the Cache Effect on Multicore Multithreaded Network ProcessorsProceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools10.1109/DSD.2008.41(317-324)Online publication date: 3-Sep-2008
https://dl.acm.org/doi/10.1109/DSD.2008.41
Rajan KGovindarajan RAltman ESkadron KZorn B(2006)Two-level mapping based cache index selection for packet forwarding enginesProceedings of the 15th international conference on Parallel architectures and compilation techniques10.1145/1152154.1152188(212-221)Online publication date: 16-Sep-2006
https://dl.acm.org/doi/10.1145/1152154.1152188

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Published In

cover image ACM Conferences

ICS '05: Proceedings of the 19th annual international conference on Supercomputing

June 2005

414 pages

ISBN:1595931678

DOI:10.1145/1088149

General Chair:
Arvind
MIT
,
Program Chair:
Larry Rudolph
MIT

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 20 June 2005

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ICS05: International Conference on Supercomputing 2005

June 20 - 22, 2005

Massachusetts, Cambridge

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Cited By

Rajan KGovindarajan R(2009)A Novel Cache Architecture and Placement Framework for Packet Forwarding EnginesIEEE Transactions on Computers10.1109/TC.2009.1858:8(1009-1025)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1109/TC.2009.18
Liu ZYu JWang XLiu BBhuyan L(2008)Revisiting the Cache Effect on Multicore Multithreaded Network ProcessorsProceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools10.1109/DSD.2008.41(317-324)Online publication date: 3-Sep-2008
https://dl.acm.org/doi/10.1109/DSD.2008.41
Rajan KGovindarajan RAltman ESkadron KZorn B(2006)Two-level mapping based cache index selection for packet forwarding enginesProceedings of the 15th international conference on Parallel architectures and compilation techniques10.1145/1152154.1152188(212-221)Online publication date: 16-Sep-2006
https://dl.acm.org/doi/10.1145/1152154.1152188

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