article

Exploring the cache design space for large scale CMPs

Authors:

Srihari Makineni,

Steve Reinhardt,

Donald NewellAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 33, Issue 4

Pages 24 - 33

https://doi.org/10.1145/1105734.1105739

Published: 01 November 2005 Publication History

Abstract

With the advent of dual-core chips in the marketplace, small-scale CMP (chip multiprocessor) architectures are becoming commonplace. We expect a continuing trend of increasing the number of cores on a die to maximize the performance/power efficiency of a single chip. We believe an era of large-scale CMPs (LCMPs) with several tens to hundreds of cores is on the way, but as of now architects have little understanding of how best to build a cache hierarchy given such a large number of cores/threads to support. With this in mind, our initial goals are to prune the cache design space for LCMPs by characterizing basic server workload behavior in such an environment.In this paper, we describe the range of methodologies that we are developing to overcome the challenges of exploring the cache design space for LCMP platforms. We then focus on employing a trace-driven approach to characterizing one key server workload (OLTP) in both a homogeneous and a heterogeneous workload environment. We study the effect of increasing threads (from 1 to 128) on a three-level cache hierarchy with emphasis on second and third level caches. We study the effect of varying sizes at these cache levels and show the effects of threads contending for cache space, the effects of prefetching instruction addresses, and the effects of inclusion. We make initial observations and conclusions about the factors on which LCMP cache hierarchy design decisions should be based and discuss future work.

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Cited By

Singh SSurana NPrasad KJain PMekie JAwasthi M(2023)HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache HierarchyACM Transactions on Architecture and Code Optimization10.1145/357283920:2(1-20)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1145/3572839
Zhou JKahn RWeiss S(2021)A novel low power hybrid cache using GC-EDRAM cellsIntegration, the VLSI Journal10.1016/j.vlsi.2021.07.00581:C(234-245)Online publication date: 1-Nov-2021
https://dl.acm.org/doi/10.1016/j.vlsi.2021.07.005
Zhao MYeung D(2017)Using Multicore Reuse Distance to Study Coherence DirectoriesACM Transactions on Computer Systems10.1145/309270235:2(1-49)Online publication date: 28-Jul-2017
https://dl.acm.org/doi/10.1145/3092702
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Exploring the cache design space for large scale CMPs

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 33, Issue 4

Special issue: dasCMP'05

November 2005

130 pages

ISSN:0163-5964

DOI:10.1145/1105734

Issue’s Table of Contents

Copyright © 2005 Authors.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 November 2005

Published in SIGARCH Volume 33, Issue 4

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Cited By

Singh SSurana NPrasad KJain PMekie JAwasthi M(2023)HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache HierarchyACM Transactions on Architecture and Code Optimization10.1145/357283920:2(1-20)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1145/3572839
Zhou JKahn RWeiss S(2021)A novel low power hybrid cache using GC-EDRAM cellsIntegration, the VLSI Journal10.1016/j.vlsi.2021.07.00581:C(234-245)Online publication date: 1-Nov-2021
https://dl.acm.org/doi/10.1016/j.vlsi.2021.07.005
Zhao MYeung D(2017)Using Multicore Reuse Distance to Study Coherence DirectoriesACM Transactions on Computer Systems10.1145/309270235:2(1-49)Online publication date: 28-Jul-2017
https://dl.acm.org/doi/10.1145/3092702
Badawy AYessin GNarayana VMayhew DEl‐Ghazawi T(2017)Optimizing thin client caches for mobile cloud computing:Concurrency and Computation: Practice and Experience10.1002/cpe.404829:11Online publication date: 3-Mar-2017
https://doi.org/10.1002/cpe.4048
Badamo MCasarona JZhao MYeung D(2016)Identifying Power-Efficient Multicore Cache Hierarchies via Reuse Distance AnalysisACM Transactions on Computer Systems10.1145/285150334:1(1-30)Online publication date: 6-Apr-2016
https://dl.acm.org/doi/10.1145/2851503
Nawinne IJavaid HRagel RRadhakrishnan SParameswaran S(2015)Exploring Multilevel Cache Hierarchies in Application Specific MPSoCsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.244573634:12(1991-2003)Online publication date: 18-Nov-2015
https://dl.acm.org/doi/10.1109/TCAD.2015.2445736
Zhao MYeung D(2015)Studying the impact of multicore processor scaling on directory techniques via reuse distance analysis2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2015.7056065(590-602)Online publication date: Feb-2015
https://doi.org/10.1109/HPCA.2015.7056065
Chaturvedi NGurunarayanan S(2015)An efficient adaptive block pinning for multicore architecturesMicroprocessors & Microsystems10.1016/j.micpro.2015.02.00639:3(181-188)Online publication date: 1-May-2015
https://dl.acm.org/doi/10.1016/j.micpro.2015.02.006
Chaturvedi NSubramaniyan AGurunarayanan S(2015)An adaptive migration---replication scheme (AMR) for shared cache in chip multiprocessorsThe Journal of Supercomputing10.1007/s11227-015-1482-071:10(3904-3933)Online publication date: 1-Oct-2015
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Yessin GBadawy ANarayana VMayhew DGhazawi T(2014)"CERE"Proceedings of the 2014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security, 2014 IEEE 11th Intl Conf on Embedded Software and Syst (HPCC,CSS,ICESS)10.1109/HPCC.2014.97(566-573)Online publication date: 20-Aug-2014
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