Article

FPGA clock network architecture: flexibility vs. area and power

Authors:

Julien Lamoureux,

Steven J. E. WiltonAuthors Info & Claims

FPGA '06: Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays

Pages 101 - 108

https://doi.org/10.1145/1117201.1117216

Published: 22 February 2006 Publication History

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Abstract

This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for Field-Programmable Gate Arrays (FPGA's). The paper begins by describing a parameterized clock network model that describes a broad range of programmable clock network architectures. Specifically, the model supports architectures with multiple local and global clock domains and varying amounts of flexibility at various levels of the clock network. Using the model, the architectural parameters that control the flexibility of the clock network are varied to determine the cost of this flexibility in terms of area and power dissipation. From these experiments, the study finds that area and power costs are highest for networks with flexibility close to the logic blocks. Furthermore, it found that clock networks with local clock domains have little overhead and are significantly more efficient than clock networks without local clock domains for applications with multiple clocks.

References

[1]

D.A. Hodges, H.G. Jackson, and R.A. Saleh, Analysis and design of digital integrated circuits: In deep submicron technology, 3rd edition, McGraw-Hill, New York, NY, 2004.

Digital Library

Google Scholar

[2]

K. Zhu, D.F. Wong, Clock skew minimization during FPGA placement, ACM/IEEE Design Automation Conference (DAC), 1994, pp. 232--237.

Digital Library

Google Scholar

[3]

Altera, Stratix II Device Handbook, Vol. 1, Chapter 2: Strattix II Architecture, March 2005.

Google Scholar

[4]

Actel, ProASIC3 Flash Family FPGAs Device Architecture, July 2005.

Google Scholar

[5]

Xilinx, Vertex-II Pro and Vertex-II Pro X Platform FPGAs: Complete Data Sheet, March 2005.

Google Scholar

[6]

V. George, H. Zang, and J. Rabaey, The design of a low-energy FPGA, Intl. Symp. on Low-Power Electronic Design (ISLPED), 1999, pp. 188--193.

Digital Library

Google Scholar

[7]

K.K.W. Poon, S.J.E Wilton, A detailed power model for field-programmable gate arrays, ACM Transactions on Design Automation of Electronic Systems (TODAES), April 2005, Vol. 10, Issue 2, 2005, pp. 279--302.

Digital Library

Google Scholar

[8]

F. Li, D. Chen, L. He, and J. Cong, Architecture evaluation for power-efficient FPGAs, Intl. Symp. on Field-Programmable Gate Arrays (FPGA), 2003, pp. 175--184.

Digital Library

Google Scholar

[9]

S. Nakamura, G. M. Masson, Lower bounds on crosspoints in concentrators, IEEE Trans. on Computers, vol. 31, no. 12, pp. 1173--1178, 1982.

Digital Library

Google Scholar

[10]

V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, 1999.

Digital Library

Google Scholar

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Bailey D(2023)Field‐programmable Gate ArraysDesign for Embedded Image Processing on FPGAs10.1002/9781119819820.ch2(19-44)Online publication date: 5-Sep-2023
https://doi.org/10.1002/9781119819820.ch2
Bouaziz KChtourou SMarrakchi ZObeid AAbid M(2022)Mesh of Trees FPGA Architecture: Exploration and OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.312054941:9(2943-2956)Online publication date: Sep-2022
https://doi.org/10.1109/TCAD.2021.3120549
Si QRashid ICarrion Schafer B(2021)Micro-architecture Tuning for Dynamic Frequency Scaling in Coarse-Grain Runtime Reconfigurable Arrays with Adaptive Clock Domain Support2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI51109.2021.00047(212-217)Online publication date: Jul-2021
https://doi.org/10.1109/ISVLSI51109.2021.00047
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Index Terms

FPGA clock network architecture: flexibility vs. area and power
1. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs

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Published In

FPGA '06: Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays

February 2006

248 pages

ISBN:1595932925

DOI:10.1145/1117201

General Chair:
Steve Wilton
University of British Columbia, Canada
,
Program Chair:
André DeHon
California Institute of Technology, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 22 February 2006

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FPGA06

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FPGA06: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 22 - 24, 2006

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Bailey D(2023)Field‐programmable Gate ArraysDesign for Embedded Image Processing on FPGAs10.1002/9781119819820.ch2(19-44)Online publication date: 5-Sep-2023
https://doi.org/10.1002/9781119819820.ch2
Bouaziz KChtourou SMarrakchi ZObeid AAbid M(2022)Mesh of Trees FPGA Architecture: Exploration and OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.312054941:9(2943-2956)Online publication date: Sep-2022
https://doi.org/10.1109/TCAD.2021.3120549
Si QRashid ICarrion Schafer B(2021)Micro-architecture Tuning for Dynamic Frequency Scaling in Coarse-Grain Runtime Reconfigurable Arrays with Adaptive Clock Domain Support2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI51109.2021.00047(212-217)Online publication date: Jul-2021
https://doi.org/10.1109/ISVLSI51109.2021.00047
Bouaziz KChtourou SMarrakchi ZObeid AAbid M(2021)A-Part: Top-Down Clustering Approach for Mesh of Clusters FPGAIntelligent Systems Design and Applications10.1007/978-3-030-71187-0_39(425-434)Online publication date: 3-Jun-2021
https://doi.org/10.1007/978-3-030-71187-0_39
Adetomi AEnemali GArslan T(2020)Enabling Dynamic Communication for Runtime Circuit RelocationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.293492728:1(142-155)Online publication date: Jan-2020
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Bouaziz KChtourou SAbid MMarrakchi ZObeid A(2019)Impact of Clustering Algorithms on the performance of Multilevel Switch Boxes FPGA with Long Wires2019 15th International Wireless Communications & Mobile Computing Conference (IWCMC)10.1109/IWCMC.2019.8766730(1025-1030)Online publication date: Jun-2019
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Chen JCarrion Schafer B(2019)Low Power Design through Frequency-Optimized Runtime Micro-Architectural Adaptation2019 IEEE 37th International Conference on Computer Design (ICCD)10.1109/ICCD46524.2019.00057(359-366)Online publication date: Nov-2019
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Bouaziz KChtourou SMarrakchi ZAbid MObeid A(2019)Exploration of Clustering Algorithms effects on Mesh of Clusters based FPGA Architecture Performance2019 International Conference on High Performance Computing & Simulation (HPCS)10.1109/HPCS48598.2019.9188138(658-665)Online publication date: Jul-2019
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Chtourou SMarrakchi ZAmouri EPangracious VAbid MMehrez H(2016)Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wiresMicroprocessors & Microsystems10.1016/j.micpro.2015.11.01140:C(16-26)Online publication date: 1-Feb-2016
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Stratix™ 10 High Performance Routable Clock Networks

Novel FPGA clock network with low latency and skew (abstract only)

Power optimization for clock network with clock gate cloning and flip-flop merging

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Stratix™ 10 High Performance Routable Clock Networks

Novel FPGA clock network with low latency and skew (abstract only)

Power optimization for clock network with clock gate cloning and flip-flop merging

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