Article

A reconfigurable hardware based embedded scheduler for buffered crossbar switches

Authors:

Lotfi Mhamdi,

Christopher Kachris, and

Stamatis VassiliadisAuthors Info & Claims

FPGA '06: Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays

February 2006

Pages 143 - 149

https://doi.org/10.1145/1117201.1117223

Published: 22 February 2006 Publication History

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Abstract

In this paper, we propose a new internally buffered crossbar (IBC) switching architecture where the input and output distributed schedulers are embedded inside the crossbar fabric chip. As opposed to previous designs, where these schedulers are spread across input and output line cards, our design allows the schedulers to have cheap and fast access to the internal buffers, optimizes the flow control mechanism and makes the IBC more scalable. We employed the Xilinx Virtex-4FX platform to show the feasibility of our proposal and implemented a reconfigurable hardware based IBC switch with the maximum port count that we could fit on a single chip. The experiments suggest that a 24x24 IBC switch running a 10 Gbps port speed and a clock cycle time of 6.4 ns can be implemented.

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Cited By

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Pan DYang Y(2012)Flow Based Performance Guarantee Scheduling in Buffered Crossbar SwitchesIEEE Transactions on Communications10.1109/TCOMM.2012.082812.10062560:12(3836-3843)Online publication date: Dec-2012
https://doi.org/10.1109/TCOMM.2012.082812.100625
Pan DMakki KPissinou N(2010)Achieve constant performance guarantees using asynchronous crossbar scheduling without speedup2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS)10.1109/IPDPS.2010.5470456(1-12)Online publication date: Apr-2010
https://doi.org/10.1109/IPDPS.2010.5470456
Skalis NMhamdi L(2010)Performance Guarantees in Partially Buffered Crossbar Switches2010 IEEE Global Telecommunications Conference GLOBECOM 201010.1109/GLOCOM.2010.5684325(1-6)Online publication date: Dec-2010
https://doi.org/10.1109/GLOCOM.2010.5684325
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Index Terms

A reconfigurable hardware based embedded scheduler for buffered crossbar switches
1. Hardware
  1. Integrated circuits
    1. Interconnect
    2. Logic circuits
2. Networks
  1. Network architectures

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Published In

FPGA '06: Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays

February 2006

248 pages

ISBN:1595932925

DOI:10.1145/1117201

General Chair:
Steve Wilton
University of British Columbia, Canada
,
Program Chair:
André DeHon
California Institute of Technology, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 February 2006

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FPGA06: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 22 - 24, 2006

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Pan DYang Y(2012)Flow Based Performance Guarantee Scheduling in Buffered Crossbar SwitchesIEEE Transactions on Communications10.1109/TCOMM.2012.082812.10062560:12(3836-3843)Online publication date: Dec-2012
https://doi.org/10.1109/TCOMM.2012.082812.100625
Pan DMakki KPissinou N(2010)Achieve constant performance guarantees using asynchronous crossbar scheduling without speedup2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS)10.1109/IPDPS.2010.5470456(1-12)Online publication date: Apr-2010
https://doi.org/10.1109/IPDPS.2010.5470456
Skalis NMhamdi L(2010)Performance Guarantees in Partially Buffered Crossbar Switches2010 IEEE Global Telecommunications Conference GLOBECOM 201010.1109/GLOCOM.2010.5684325(1-6)Online publication date: Dec-2010
https://doi.org/10.1109/GLOCOM.2010.5684325
Pan DMakki KPissinou N(2009)Fair queueing based packet scheduling for buffered crossbar switchesProceedings of the 28th IEEE conference on Global telecommunications10.5555/1811380.1811644(1592-1597)Online publication date: 30-Nov-2009
https://dl.acm.org/doi/10.5555/1811380.1811644
Mhamdi L(2009)PBCIEEE Transactions on Computers10.1109/TC.2009.6558:11(1568-1581)Online publication date: 1-Nov-2009
https://dl.acm.org/doi/10.1109/TC.2009.65
Pan DYang Y(2009)Localized Independent Packet Scheduling for Buffered Crossbar SwitchesIEEE Transactions on Computers10.1109/TC.2008.14058:2(260-274)Online publication date: 1-Feb-2009
https://dl.acm.org/doi/10.1109/TC.2008.140
Pan DMakki KPissinou N(2009)Fair Queueing Based Packet Scheduling for Buffered Crossbar SwitchesGLOBECOM 2009 - 2009 IEEE Global Telecommunications Conference10.1109/GLOCOM.2009.5425680(1-6)Online publication date: Nov-2009
https://doi.org/10.1109/GLOCOM.2009.5425680
Pan DYang ZMakki KPissinou N(2009)Providing Performance Guarantees for Buffered Crossbar Switches without SpeedupQuality of Service in Heterogeneous Networks10.1007/978-3-642-10625-5_19(297-314)Online publication date: 2009
https://doi.org/10.1007/978-3-642-10625-5_19
Mhamdi L(2008)A Partially Buffered Crossbar packet switching architecture and its scheduling2008 IEEE Symposium on Computers and Communications10.1109/ISCC.2008.4625643(942-948)Online publication date: Jul-2008
https://doi.org/10.1109/ISCC.2008.4625643

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Localized Independent Packet Scheduling for Buffered Crossbar Switches

Self-Reconfigurable Embedded Systems on Low-Cost FPGAs

Smooth switching problem in buffered crossbar switches

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Localized Independent Packet Scheduling for Buffered Crossbar Switches

Self-Reconfigurable Embedded Systems on Low-Cost FPGAs

Smooth switching problem in buffered crossbar switches

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