FPGAs with multidimensional mesh topology

In a traditional 2-D field-programmable gate array (FPGA), the number of routing switches increases as the number of logic gates increases, and thereby causes a decrease in the logic density. DeHon et al. demonstrated that a tree-based FPGA they proposed resolves this problem and requires only a constant number ofswitches per gate without any relation to the total number of gates. This paper presents that a multidimensional FPGA that exploits the multidimensional mesh topology also achieves asymptotically identical area efficiency to that of a tree-based FPGA. We model a multidimensional FPGA as a simple extension of the traditional 2-D and 3-D FPGAs, and realize it by embedding it onto a 2-D chip. We show a multidimensional FPGA can be embedded onto a 2-D chip with no critical increase in the amount of metal wiring. Although our embedding method causes a gap between the lengths of wire segments in different axial directions, a multidimensional FPGA indicates lower interconnection delay than a 2-D FPGA. We show that the speed advantage of a 4-D FPGA compared with a 2-D FPGA extends along with further integration and scaling of semiconductor devices by predicting maximum and average net delays.