Configuration tools for a new multilevel hierarchical FPGA
Abstract
Index Terms
- Configuration tools for a new multilevel hierarchical FPGA
Recommendations
Multilevel optimization for large-scale hierarchical FPGA placement
This paper proposes a multilevel placer targeted at hierarchical FPGA (Field Programmable Gate Array) devices. The placer is based on multilevel optimization method which combines the multilevel bottom-up clustering process and top-down placement ...
A multilevel hierarchical interconnection structure for FPGA
FPGA '06: Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arraysCreation of large FPGAs needs radical efficient changes in architecture to improve speed, density and software mapping time. Based on industry experience with standard ASICs, we believe that partitioning and hierarchy become an obligation for FPGA ...
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure
ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided designThis paper presents a new Multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-Fat-Tree topology, and an upward network using hierarchy. Studies ...
Comments
Information & Contributors
Information
Published In
![cover image ACM Conferences](/cms/asset/fd9c4a91-74f1-4095-9492-86582f039655/1117201.cover.jpg)
Sponsors
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Check for updates
Qualifiers
- Article
Conference
Acceptance Rates
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Other Metrics
Citations
View Options
Get Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in