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FPGA based RAID 6 hardware accelerator

Authors:

Michael Gilroy,

James Irvine, and

William BerrieAuthors Info & Claims

FPGA '06: Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays

February 2006

Page 232

https://doi.org/10.1145/1117201.1117254

Published: 22 February 2006 Publication History

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Abstract

Hard disk storage capacity has continued to rise whilst at the same time the cost per megabyte continues to fall. This, combined with increased usage of digital storage for documents, photography and video for both home and business use has led to increased need for reliable data storage system. Redundant arrays of inexpensive disks (RAID) have proven to offer the best characteristics for reliable storage. However, to date RAID based systems have been limited by their support for only single disk erasure tolerance.This paper introduces an efficient hardware RAID 6 controller on an FPGA capable offering support for uninterrupted access during double disk erasures and recovery.

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Jayaraman RKartadihardja HMaskell D(2011)Performance-Power Design Space Exploration in a Hybrid Computing Platform Suitable for Mobile ApplicationsProceedings of the 2011 International Symposium on Electronic System Design10.1109/ISED.2011.55(140-145)Online publication date: 19-Dec-2011
https://dl.acm.org/doi/10.1109/ISED.2011.55
Sobe PHampel V(2007)FPGA-accelerated deletion-tolerant coding for reliable distributed storageProceedings of the 20th international conference on Architecture of computing systems10.5555/1763274.1763276(14-27)Online publication date: 12-Mar-2007
https://dl.acm.org/doi/10.5555/1763274.1763276

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FPGA based RAID 6 hardware accelerator
1. Hardware

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FPGA '06: Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays

February 2006

248 pages

ISBN:1595932925

DOI:10.1145/1117201

General Chair:
Steve Wilton
University of British Columbia, Canada
,
Program Chair:
André DeHon
California Institute of Technology, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 22 February 2006

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FPGA06

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FPGA06: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 22 - 24, 2006

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Jayaraman RKartadihardja HMaskell D(2011)Performance-Power Design Space Exploration in a Hybrid Computing Platform Suitable for Mobile ApplicationsProceedings of the 2011 International Symposium on Electronic System Design10.1109/ISED.2011.55(140-145)Online publication date: 19-Dec-2011
https://dl.acm.org/doi/10.1109/ISED.2011.55
Sobe PHampel V(2007)FPGA-accelerated deletion-tolerant coding for reliable distributed storageProceedings of the 20th international conference on Architecture of computing systems10.5555/1763274.1763276(14-27)Online publication date: 12-Mar-2007
https://dl.acm.org/doi/10.5555/1763274.1763276

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RAID 6 Hardware Acceleration

A Hybrid Approach to Failed Disk Recovery Using RAID-6 Codes: Algorithms and Performance Evaluation

Hybrid S-RAID: A Power-Aware Archival Storage Architecture

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RAID 6 Hardware Acceleration

A Hybrid Approach to Failed Disk Recovery Using RAID-6 Codes: Algorithms and Performance Evaluation

Hybrid S-RAID: A Power-Aware Archival Storage Architecture

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