Article

Programmable numerical function generators based on quadratic approximation: architecture and synthesis method

Authors:

Shinobu Nagayama,

Jon T. ButlerAuthors Info & Claims

ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Pages 378 - 383

https://doi.org/10.1145/1118299.1118394

Published: 24 January 2006 Publication History

Abstract

This paper presents an architecture and a synthesis method for programmable numerical function generators (NFGs) for trigonometric, logarithmic, square root, and reciprocal functions. Our NFG partitions a given domain of the function into non-uniform segments using an LUT cascade, and approximates the given function by a quadratic polynomial for each segment. Thus, we can implement fast and compact NFGs for a wide range of functions. Implementation results on an FPGA show that: 1) our NFGs require only 4% of the memory needed by NFGs based on the linear approximation with non-uniform segmentation; and 2) our NFGs require only 22% of the memory needed by NFGs based on the 5th-order approximation with uniform segmentation. Our automatic synthesis system generates such compact NFGs quickly.

References

[1]

R. Andraka, "A survey of CORDIC algorithms for FPGA based computers," Proc. of the 1998 ACM/SIGDA Sixth Inter. Symp. on Field Programmable Gate Array (FPGA'98), pp. 191--200, Monterey, CA, Feb. 1998.

Digital Library

[2]

J. Cao, B. W. Y. Wei, and J. Cheng, "High-performance architectures for elementary function generation," Proc. of the 15th IEEE Symp. on Computer Arithmetic (ARITH'01), Vail, Co, pp. 136--144, June 2001.

Digital Library

[3]

D. Defour, F. de Dinechin, and J.-M. Muller, "A new scheme for table-based evaluation of functions," 36th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, pp. 1608--1613, Nov. 2002.

[4]

J. Detrey and F. de Dinechin, "Second order function approximation using a single multiplication on FPGAs," Proc. Inter. Conf. on Field Programmable Logic and Applications (FPL'04), pp. 221--230, 2004.

[5]

N. Doi, T. Horiyama, M. Nakanishi, and S. Kimura, "Minimization of fractional wordlength on fixed-point conversion for high-level synthesis," Proc. of Asia and South Pacific Design Automation Conference (ASPDAC'04), pp. 80--85, 2004.

Digital Library

[6]

H. Hassler and N. Takagi, "Function evaluation by table look-up and addition," Proc. of the 12th IEEE Symp. on Computer Arithmetic (ARITH'95), Bath, England, pp. 10--16, July 1995.

Digital Library

[7]

T. Ibaraki and M. Fukushima, FORTRAN 77 Optimization Programming, Iwanami, 1991 (in Japanese).

[8]

Y. Iguchi, T. Sasao, and M. Matsuura, "Realization of multiple-output functions by reconfigurable cascades," International Conference on Computer Design: VLSI in Computers and Processors (ICCD'01), Austin, TX, pp. 388--393, Sept. 23--26, 2001.

Digital Library

[9]

D.-U. Lee, W. Luk, J. Villasenor, and P. Y. K. Cheung, "Non-uniform segmentation for hardware function evaluation," Proc. Inter. Conf. on Field Programmable Logic and Applications, pp. 796--807, Lisbon, Portugal, Sept. 2003.

[10]

D.-U. Lee, W. Luk, J. Villasenor, and P. Y. K. Cheung, "A hardware Gaussian noise generator for channel code evaluation," Proc. of the 11th Annual IEEE Symp. on Field-Programmable Custom Computing Machines (FCCM'03), Napa, CA, pp. 69--78, April 2003.

Digital Library

[11]

J. H. Mathews, Numerical Methods for Computer Science, Engineering and Methematics, Prentice-Hall, Inc., Englewood Cliffs, NJ, 1987.

Digital Library

[12]

J.-M. Muller, Elementary Function: Algorithms and Implementation, Birkhauser Boston, Inc., Secaucus, NJ, 1997.

Digital Library

[13]

S. Nagayama and T. Sasao, "Compact representations of logic functions using heterogeneous MDDs," IEICE Trans. on fundamentals, Vol. E86-A, No. 12, pp. 3168--3175, Dec. 2003.

[14]

S. Nagayama, T. Sasao, and J. T. Butler, "Error analysis for programmable numerical function generators based on quadratic approximation," http://www.lsi-cad.com/Error-QNFG/.

[15]

T. Sasao, M. Matsuura, and Y. Iguchi, "A cascade realization of multiple-output function for reconfigurable hardware," Inter. Workshop on Logic Synthesis (IWLS'01), Lake Tahoe, CA, pp. 225--230, June 12--15, 2001.

[16]

T. Sasao, J. T. Butler, and M. D. Riedel, "Application of LUT cascades to numerical function generators," Proc. the 12th workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'04), Kanazawa, Japan, pp. 422--429, Oct. 2004.

[17]

T. Sasao, S. Nagayama, and J. T. Butler, "Programmable numerical function generators: architectures and synthesis method," Proc. Inter. Conf. on Field Programmable Logic and Applications (FPL'05), Tampare, Finland, pp. 118--123, Aug. 2005.

[18]

Scilab 3.0 INRIA-ENPC, France, http://scilabsoft.inria.fr/

[19]

M. J. Schulte and J. E. Stine, "Approximating elementary functions with symmetric bipartite tables," IEEE Trans. on Comp., Vol. 48, No. 8, pp. 842--847 Aug. 1999.

Digital Library

[20]

J. E. Stine and M. J. Schulte, "The symmetric table addition method for accurate function approximation," Jour. of VLSI Signal Processing, Vol. 21, No. 2, pp. 167--177, June 1999.

Digital Library

[21]

J. E. Volder, "The CORDIC trigonometric computing technique," IRE Trans. Electronic Comput., Vol. EC-820, No. 3, pp. 330--334, Sept. 1959.

Cited By

He CYan BXu SZhang YWang ZWang M(2023)Research and Hardware Implementation of a Reduced-Latency Quadruple-Precision Floating-Point Arctangent AlgorithmElectronics10.3390/electronics1216347212:16(3472)Online publication date: 16-Aug-2023
https://doi.org/10.3390/electronics12163472
HOANG VPHAM C(2013)Low Complexity Logarithmic and Anti-Logarithmic Converters for Hybrid Number System Processors and DSP ApplicationsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E96.A.584E96.A:2(584-590)Online publication date: 2013
https://doi.org/10.1587/transfun.E96.A.584
Hsiao SKo HTseng YHuang WLin SWen C(2013)Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address RemappingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.220229521:5(875-886)Online publication date: 1-May-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2202295
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Index Terms

Programmable numerical function generators based on quadratic approximation: architecture and synthesis method
1. Hardware

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Published In

cover image ACM Conferences

ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference

January 2006

998 pages

ISBN:0780394518

General Chair:
Fumiyasu Hirose
Cadence Design Systems, Japan

Sponsors

IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

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IEEE Press

Publication History

Published: 24 January 2006

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

He CYan BXu SZhang YWang ZWang M(2023)Research and Hardware Implementation of a Reduced-Latency Quadruple-Precision Floating-Point Arctangent AlgorithmElectronics10.3390/electronics1216347212:16(3472)Online publication date: 16-Aug-2023
https://doi.org/10.3390/electronics12163472
HOANG VPHAM C(2013)Low Complexity Logarithmic and Anti-Logarithmic Converters for Hybrid Number System Processors and DSP ApplicationsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E96.A.584E96.A:2(584-590)Online publication date: 2013
https://doi.org/10.1587/transfun.E96.A.584
Hsiao SKo HTseng YHuang WLin SWen C(2013)Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address RemappingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.220229521:5(875-886)Online publication date: 1-May-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2202295
Hoang VDo XPham C(2013)An efficient ASIC implementation of logarithm approximation for HDR image processing2013 International Conference on Advanced Technologies for Communications (ATC 2013)10.1109/ATC.2013.6698173(535-539)Online publication date: Oct-2013
https://doi.org/10.1109/ATC.2013.6698173
Kim YKim HKim SPark JPaek SKim L(2012)Homogeneous stream processors with embedded special function units for high-utilization programmable shadersIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.216149920:9(1691-1704)Online publication date: 1-Sep-2012
https://dl.acm.org/doi/10.1109/TVLSI.2011.2161499
Lee DCheung RLuk WVillasenor J(2009)Hierarchical segmentation for hardware function evaluationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200316517:1(103-116)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2003165
Sasao TNagayama SButler J(2007)Numerical Function Generators Using LUT CascadesIEEE Transactions on Computers10.1109/TC.2007.103356:6(826-838)Online publication date: 1-Jun-2007
https://dl.acm.org/doi/10.1109/TC.2007.1033
Nagayama SSasao TButler J(2007)Numerical Function Generators Using Edge-Valued Binary Decision DiagramsProceedings of the 2007 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2007.358041(535-540)Online publication date: 23-Jan-2007
https://dl.acm.org/doi/10.1109/ASPDAC.2007.358041

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