Article

Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems

Authors:

Sanjay V. Kumar,

Chris H. Kim,

Sachin S. SapatnekarAuthors Info & Claims

ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Pages 559 - 564

https://doi.org/10.1145/1118299.1118433

Published: 24 January 2006 Publication History

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Abstract

Process variations and temperature variations can cause both the frequency and the leakage of the chip to vary significantly from their expected values, thereby decreasing the yield. Adaptive Body Bias (ABB) can be used to pull back the chip to the nominal operational region. We propose the use of this technique to counter temperature variations along with process variations. We present a CAD perspective for achieving process and temperature compensation using bidirectional ABB. Mathematical models are used to determine the exact amount of body bias required to optimize the delay and leakage, and an algorithmic flow that can be adopted for gigascale LSI systems is provided.

References

[1]

T. Chen and S. Naffziger. "Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation". In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pages 888--899, October 2003.

Digital Library

Google Scholar

[2]

C. H. Wann, H. Chenming, K. Noda, D. Sinitsky, F. Assaderaghi, and J. Bokor, "Channel doping engineering of MOSFET with adaptable threshold voltage using body effect for low voltage and low power applications". In International Symposium of VLSI Technology, pages 159--163, June 1995.

Crossref

Google Scholar

[3]

T. Kuroda, T. Fujita, S. Mita, T. Nagamatu, S. Yoshioka, F. Sano, M. Norishima, M. Murota. M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai. "A 0.9 V 150 MHz 10 mW 2-D discrete cosine transform core processor with variable-threshold-voltage scheme". In IEEE International Solid-State Circuits Conference, pages 166--167, August 1996.

Google Scholar

[4]

J. W. Tschanz, J. T. Kao, S. G. Narendra, R. Nair, D. A. Antoniadis, A. P. Chandrakasan, and V. De. "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage". IEEE Journal of Solid-State Circuits, 37(11):1396--1402, November 2002.

Crossref

Google Scholar

[5]

J. W. Tschanz, S. G. Narendra, Y. Ye, B. A. Bloechel, S. Borkar, and V. De. "Dynamic sleep transistor and body bias for active leakage power control of microprocessors". IEEE Journal of Solid-State Circuits, 38(11):1838--1845, November 2003.

Crossref

Google Scholar

[6]

J. W. Tschanz, S. G. Narendra, R. Nair, and V. De. "Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors". IEEE Journal of Solid-State Circuits, 38(5):826--829, May 2003.

Crossref

Google Scholar

[7]

S. Narendra, A. Keshavarzi, B. A. Bloechel, S. Borkar, and V. De. "Forward body bias for microprocessors in 130-nm technology generation and beyond". IEEE Journal of Solid-State Circuits, 38(5):696--701, May 2003.

Crossref

Google Scholar

[8]

G. Ono, M. Miyazaki, H. Tanaka, N. Ohkubo, and T. Kawahara. "Temperature referenced supply voltage and forward-body-bias control (TSFC) architecture for minimum power consumption". In European Solid State Circuits Conference, pages 391--394, September 2004.

Crossref

Google Scholar

[9]

T. Kuroda. "Low power CMOS digital design for multimedia processors". In International Conference for VLSI and CAD, pages 359--367, October 1999.

Google Scholar

[10]

Device Group at UC Berkeley. "Berkeley Predictive Technology Model", 2002. Available at http://www-device.eecs.berkeley.edu/~ptm/.

Google Scholar

[11]

H. Ananthan, C. H. Kim, and K. Roy. "Larger-than-Vdd forward body bias in sub-0.5V nanoscale CMOS". In International Symposium on Low Power Electronic Design, pages 8--13, 2004.

Digital Library

Google Scholar

[12]

E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli. "SIS: A system for sequential circuit synthesis". Technical Report UCB/ERL M92/41, 1992. Available at http://www-cad.eecs.berkeley.edu/research/sis.

Google Scholar

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Narczyk PPleskacz W(2022)Analog Frontend for Reliable Human Body Temperature Measurement for IoT DevicesElectronics10.3390/electronics1103043411:3(434)Online publication date: 31-Jan-2022
https://doi.org/10.3390/electronics11030434
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Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems

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ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference

January 2006

998 pages

ISBN:0780394518

General Chair:
Fumiyasu Hirose
Cadence Design Systems, Japan

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IEEE Press

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Published: 24 January 2006

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Narczyk PPleskacz W(2022)Analog Frontend for Reliable Human Body Temperature Measurement for IoT DevicesElectronics10.3390/electronics1103043411:3(434)Online publication date: 31-Jan-2022
https://doi.org/10.3390/electronics11030434
Ganapathy SCanal RGonzalez ARubio AOklobdzija VPangle BChang NShanbhag NKim C(2010)MODESTProceedings of the 16th ACM/IEEE international symposium on Low power electronics and design10.1145/1840845.1840873(129-134)Online publication date: 18-Aug-2010
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Ghosh S(2010)Effect of Variations and Variation Tolerance in Logic CircuitsLow-Power Variation-Tolerant Design in Nanometer Silicon10.1007/978-1-4419-7418-1_3(83-108)Online publication date: 25-Oct-2010
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Sathanur APullini ABenini LDe Micheli GMacii EBenini LDe Micheli GAl-Hashimi BMueller W(2009)Physically clustered forward body biasing for variability compensation in nanometer CMOS designProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874658(154-159)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874658
Liu QSapatnekar S(2009)A framework for scalable postsilicon statistical delay prediction under process variationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.202173228:8(1201-1212)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2021732
Qi ZStan MNarayanan VYan ZMacii EBhanja S(2008)NBTI resilient circuits using adaptive body biasingProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366179(285-290)Online publication date: 4-May-2008
https://dl.acm.org/doi/10.1145/1366110.1366179
Kulkarni SSylvester DBlaauw D(2008)Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body BiasIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.91552927:3(481-494)Online publication date: 1-Mar-2008
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Liu QSapatnekar SLevitan S(2007)Confidence scalable post-silicon statistical delay prediction under process variationsProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278609(497-502)Online publication date: 4-Jun-2007
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Zhan YGoplen BSapatnekar SHirose F(2006)Electrothermal analysis and optimization techniques for nanoscale integrated circuitsProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118359(219-222)Online publication date: 24-Jan-2006
https://dl.acm.org/doi/10.1145/1118299.1118359

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Body bias voltage computations for process and temperature compensation

Temperature-adaptive voltage scaling for enhanced energy efficiency in subthreshold memory arrays

On-chip process variations compensation using an analog adaptive body bias (A-ABB)

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Body bias voltage computations for process and temperature compensation

Temperature-adaptive voltage scaling for enhanced energy efficiency in subthreshold memory arrays

On-chip process variations compensation using an analog adaptive body bias (A-ABB)

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