Article

Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability

Authors:

Ashish Goel,

Swarup Bhunia,

Hamid Mahmoodi,

Kaushik RoyAuthors Info & Claims

ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Pages 665 - 670

https://doi.org/10.1145/1118299.1118456

Published: 24 January 2006 Publication History

Get Access

Abstract

With technology scaling, soft error resilience is becoming a major concern in circuit design. This paper presents a class of low-overhead flip-flops suitable for soft error detection and correction. The proposed design reuses logic elements typically available in a standard-cell implementation of a flip-flop to reduce hardware overhead. We demonstrate that the proposed flip-flops are also suitable for enhanced scan based delay fault testing, which allows arbitrary two-pattern test application for the best combinational path testability. The proposed flip-flops show an average power reduction of 16% and area improvement of 17% compared to the best alternative techniques with no additional delay overhead.

References

[1]

T. Karnik, P. Hazucha, J. Patel, "Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes," IEEE Transactions on Dependable and Secure Computing, Vol. 1, No. 2, April-June 2004.

Digital Library

Google Scholar

[2]

P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, L. Alvisi, "Modeling the effect of technology trends on the soft error rate of combinational logic," International Conference on Dependable Systems and Networks, 2002, pp. 389--398.

Digital Library

Google Scholar

[3]

P. Hazucha et al, "Measurements and Analysis of SER-Tolerant Latch in a 90-nm Dual-VT CMOS Process", IEEE Journal of Solid-State Circuits, Vol. 39, No. 9, September 2004.

Crossref

Google Scholar

[4]

R. Ramanarayanan, V. Degalahal, N. Vijaykrishnan, M. J. Irwin, D. Duarte, "Analysis of Soft Error Rate in Flip-Flops and Scannable Latches," IEEE SOC Conference, Sept. 2003, pp. 231--234.

Google Scholar

[5]

Q. Zhaou, K. Mohanram, "Cost-Effective Radiation Hardening Technique for Combinational Logic," ICCAD, 2004, pp. 100--106.

Digital Library

Google Scholar

[6]

W. Mao et al., "Reducing correlation to improve coverage of delay faults in scan-path design," IEEE Transactions on CAD, Vol. 13, No. 5, May 1994 pp. 638--646.

Digital Library

Google Scholar

[7]

M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits, Kluwer Academic Publishers, 2000.

Google Scholar

[8]

R. Kuppuswamy et al., "Full Hold-Scan Systems in Microprocessors: Cost/Benefit Analysis," Intel Technology Journal, Vol. 8, Issue 1, Feb. 2004.

Google Scholar

[9]

S. Mitra, N. Seifert, M. Zhang, Q. Shi, K. Kim. "Robust System Design with Built-In Soft-Error Resilience," Computer, vol. 38, No. 2, Feb. 2005, pp. 43--52.

Digital Library

Google Scholar

[10]

J. Tschanz et al, "Comparative Delay and Energy of Single Edge-Trigerred & Dual Edge-Triggered Pulsed Flip-Flops for High-Performance Microprocessors," ISLPED, 2001, pp. 147--152

Digital Library

Google Scholar

[11]

University of California, Predictive Technology Model, http://www.device.eecs.berkeley.edu/~ptm, 2001.

Google Scholar

[12]

Artisan Standard Cell Library for 0.13-micron TSMC process, http://www.artisan.com/products/standardcell.html

Google Scholar

Cited By

View all

MA RHOLST SWEN XYAN AXU H(2022)Evaluation and Test of Production Defects in Hardened LatchesIEICE Transactions on Information and Systems10.1587/transinf.2021EDP7216E105.D:5(996-1009)Online publication date: 1-May-2022
https://doi.org/10.1587/transinf.2021EDP7216
Lin DWen C(2021)A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault TestabilityACM Transactions on Design Automation of Electronic Systems10.1145/346217126:6(1-12)Online publication date: 28-Jun-2021
https://dl.acm.org/doi/10.1145/3462171
Hemmat MKamal MAfzali-Kusha APedram M(2017)Hybrid TFET-MOSFET circuitIntegration, the VLSI Journal10.1016/j.vlsi.2016.11.00157:C(11-19)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.11.001
Show More Cited By

Index Terms

Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability
1. Hardware

Recommendations

Flip-Flops for Multiple-Valued Logic

A family of multiple-valued (MV) electronic memory elements, referred to herein as flip-flops, is presented along with a system of MV algebra upon which they are based. These MV flip-flops are compared to binary flip-flops. MV asynchronous set-clear ...
ATPG for scan chain latches and flip-flops
VTS '97: Proceedings of the 15th IEEE VLSI Test Symposium

A new approach for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking experiment to each bistable element in the circuit while checking their ...
Selecting partial scan flip-flops for circuit partitioning
ICCAD '94: Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

This paper presents a new method of selecting scan flip-flops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned into many small subcircuits which can be dealt with separately by a test ...

Comments

Information & Contributors

Information

Published In

ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference

January 2006

998 pages

ISBN:0780394518

General Chair:
Fumiyasu Hirose
Cadence Design Systems, Japan

Publisher

IEEE Press

Publication History

Published: 24 January 2006

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

4
Total Citations
View Citations
260
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 25 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

MA RHOLST SWEN XYAN AXU H(2022)Evaluation and Test of Production Defects in Hardened LatchesIEICE Transactions on Information and Systems10.1587/transinf.2021EDP7216E105.D:5(996-1009)Online publication date: 1-May-2022
https://doi.org/10.1587/transinf.2021EDP7216
Lin DWen C(2021)A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault TestabilityACM Transactions on Design Automation of Electronic Systems10.1145/346217126:6(1-12)Online publication date: 28-Jun-2021
https://dl.acm.org/doi/10.1145/3462171
Hemmat MKamal MAfzali-Kusha APedram M(2017)Hybrid TFET-MOSFET circuitIntegration, the VLSI Journal10.1016/j.vlsi.2016.11.00157:C(11-19)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.11.001
NAMBA KITO H(2011)Construction of BILBO FF with Soft-Error-Tolerant CapabilityIEICE Transactions on Information and Systems10.1587/transinf.E94.D.1045E94-D:5(1045-1050)Online publication date: 2011
https://doi.org/10.1587/transinf.E94.D.1045

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Abstract

References

Cited By

Index Terms

Recommendations

Flip-Flops for Multiple-Valued Logic

ATPG for scan chain latches and flip-flops

Selecting partial scan flip-flops for circuit partitioning

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Acceptance Rates

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Login options

Full Access

View options

PDF

eReader

Share

Share this Publication link

Share on social media

Affiliations