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Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration

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Ahmed A. JerrayaAuthors Info & Claims

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Pages 969 - 972

https://doi.org/10.1145/1120725.1120769

Published: 18 January 2005 Publication History

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Abstract

Current and future SoC will contain an increasing number of heterogeneous multiprocessor subsystems combined with a complex communication architecture to meet flexibility, performance and cost constraints. The early validation of such complex MP-SoC architectures is a key enabler to manage this complexity and thus to enhance design productivity.In this paper, we describe an abstract, high level CPU subsystem model that captures the specificities of such MP-SoC architectures, along with a timed co-simulation environment to perform early exploration of the entire HW/SW design. The model is based on the Hardware Abstraction Layer (HAL) concept allowing the validation of complex applications written on top of real-life operating systems. Experimentation with a MPEG4 application proves the interest of the proposed methodology.

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Mueller-Gritschneder DGerstlauer A(2017)Host-Compiled SimulationHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_18-1(1-27)Online publication date: 8-Apr-2017
https://doi.org/10.1007/978-94-017-7358-4_18-1
Mueller-Gritschneder DGerstlauer A(2017)Host-Compiled SimulationHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_18(593-619)Online publication date: 27-Sep-2017
https://doi.org/10.1007/978-94-017-7267-9_18
Bringmann OEcker WGerstlauer AGoyal AMueller-Gritschneder DSasidharan PSingh SNebel WAtienza D(2015)The next generation of virtual prototypingProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757206(1698-1707)Online publication date: 9-Mar-2015
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ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

January 2005

1495 pages

ISBN:0780387376

DOI:10.1145/1120725

General Chair:
Ting-Ao Tang
Fudan University, Shanghai, P. R. China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 18 January 2005

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ASPDAC05: Asia and South Pacific Design Automation Conference

January 18 - 21, 2005

Shanghai, China

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Mueller-Gritschneder DGerstlauer A(2017)Host-Compiled SimulationHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_18-1(1-27)Online publication date: 8-Apr-2017
https://doi.org/10.1007/978-94-017-7358-4_18-1
Mueller-Gritschneder DGerstlauer A(2017)Host-Compiled SimulationHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_18(593-619)Online publication date: 27-Sep-2017
https://doi.org/10.1007/978-94-017-7267-9_18
Bringmann OEcker WGerstlauer AGoyal AMueller-Gritschneder DSasidharan PSingh SNebel WAtienza D(2015)The next generation of virtual prototypingProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757206(1698-1707)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2757206
Hamayun MPetrot FFournel N(2013)Native simulation of complex VLIW instruction sets using static binary translation and Hardware-Assisted Virtualization2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2013.6509660(576-581)Online publication date: Jan-2013
https://doi.org/10.1109/ASPDAC.2013.6509660
Wu MWang PFu CTsay R(2012)An Extended SystemC Framework for Efficient HW/SW Co-SimulationACM Transactions on Design Automation of Electronic Systems10.1145/2159542.215954317:2(1-16)Online publication date: 1-Apr-2012
https://dl.acm.org/doi/10.1145/2159542.2159543
Ihmig MFeilen MHerkersdorf A(2012)Analytical Design Space Exploration Based on Statistically Refined Runtime and Logic Estimation for Software Defined RadiosProceedings of the 2012 15th Euromicro Conference on Digital System Design10.1109/DSD.2012.23(445-452)Online publication date: 5-Sep-2012
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Kempf TAscheid GLeupers RKempf TAscheid GLeupers R(2011)MethodologyMultiprocessor Systems on Chip10.1007/978-1-4419-8153-0_5(55-65)Online publication date: 10-Jan-2011
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Schirner GGerstlauer ADömer RLin Y(2010)System-level development of embedded softwareProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899927(903-909)Online publication date: 18-Jan-2010
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Gerstlauer ASchirner GLin Y(2010)Platform modeling for exploration and synthesisProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899889(725-731)Online publication date: 18-Jan-2010
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Schirner GGerstlauer ADömer R(2010)Fast and accurate processor models for efficient MPSoC designACM Transactions on Design Automation of Electronic Systems10.1145/1698759.169876015:2(1-26)Online publication date: 2-Mar-2010
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HW/SW implementation from abstract architecture models

Fast and accurate timed execution of high level embedded software using HW/SW interface simulation model

HW/SW Co-design of an IEEE 802.11a/g Receiver on Xilinx Zynq SoC using High-Level Synthesis

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