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Automated throughput-driven synthesis of bus-based communication architectures

Published: 18 January 2005 Publication History

Abstract

As System-on-Chip (SoC) designs become more complex, it becomes increasingly harder to design communication architectures which satisfy design constraints. Manually traversing the vast communication design space for constraint-driven synthesis is not feasible anymore. In this paper we propose an approach that automates the synthesis of bus-based communication architectures for systems characterized by (possibly several) throughput constraints. Our approach accurately and effectively prunes the large communication design space to synthesize a feasible low-cost bus architecture which satisfies the constraints in a design.

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Cited By

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  • (2008)Synthesis of On-Chip Communication ArchitecturesOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00006-2(185-252)Online publication date: 2008
  • (2006)Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applicationsProceedings of the 4th international conference on Hardware/software codesign and system synthesis10.1145/1176254.1176326(294-299)Online publication date: 22-Oct-2006
  • (2006)Contentions-conscious dynamic but deterministic scheduling of computational and communication tasksProceedings of the 2006 ACM symposium on Applied computing10.1145/1141277.1141623(1487-1492)Online publication date: 23-Apr-2006
  • Show More Cited By

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cover image ACM Conferences
ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference
January 2005
1495 pages
ISBN:0780387376
DOI:10.1145/1120725
  • General Chair:
  • Ting-Ao Tang
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 18 January 2005

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Cited By

View all
  • (2008)Synthesis of On-Chip Communication ArchitecturesOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00006-2(185-252)Online publication date: 2008
  • (2006)Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applicationsProceedings of the 4th international conference on Hardware/software codesign and system synthesis10.1145/1176254.1176326(294-299)Online publication date: 22-Oct-2006
  • (2006)Contentions-conscious dynamic but deterministic scheduling of computational and communication tasksProceedings of the 2006 ACM symposium on Applied computing10.1145/1141277.1141623(1487-1492)Online publication date: 23-Apr-2006
  • (2006)Constraint-driven bus matrix synthesis for MPSoCProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118309(30-35)Online publication date: 24-Jan-2006

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