Article

A fast digit-serial systolic multiplier for finite field GF(2^m)

Authors:

Chang Hoon Kim,

Soonhak Kwon,

Chun Pyo HongAuthors Info & Claims

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Pages 1268 - 1271

https://doi.org/10.1145/1120725.1121040

Published: 18 January 2005 Publication History

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Abstract

This paper presents a new digit-serial systolic multiplier over GF(2^m) for cryptographic applications. When input data come in continuously, the proposed array produces multiplication results at a rate of one every [m/D] + 2 clock cycles, where D is the selected digit size. Since the inner structure of the proposed array is tree-type, critical path increases logarithmically proportional to D. Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to D. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementations.

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Pradhan DMeher BMeher P(2023)Digit-Size Selection for FPGA Implementation of Generic Digit-Serial Multiplication Over GF(2m)2023 1st International Conference on Circuits, Power and Intelligent Systems (CCPIS)10.1109/CCPIS59145.2023.10291975(1-6)Online publication date: 1-Sep-2023
https://doi.org/10.1109/CCPIS59145.2023.10291975
Rashidi B(2020)Throughput/Area Efficient Implementation of Scalable Polynomial Basis MultiplicationJournal of Hardware and Systems Security10.1007/s41635-019-00087-5Online publication date: 2-Jan-2020
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Long JKu JMemik SIsmail Y(2018)SACTAIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202399218:9(1323-1336)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2009.2023992
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A fast digit-serial systolic multiplier for finite field GF(2^m)
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Published In

ASP-DAC '05: Proceedings of the 2005 Asia and South Pacific Design Automation Conference

January 2005

1495 pages

ISBN:0780387376

DOI:10.1145/1120725

General Chair:
Ting-Ao Tang
Fudan University, Shanghai, P. R. China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 18 January 2005

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ASPDAC05: Asia and South Pacific Design Automation Conference

January 18 - 21, 2005

Shanghai, China

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

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Pradhan DMeher BMeher P(2023)Digit-Size Selection for FPGA Implementation of Generic Digit-Serial Multiplication Over GF(2m)2023 1st International Conference on Circuits, Power and Intelligent Systems (CCPIS)10.1109/CCPIS59145.2023.10291975(1-6)Online publication date: 1-Sep-2023
https://doi.org/10.1109/CCPIS59145.2023.10291975
Rashidi B(2020)Throughput/Area Efficient Implementation of Scalable Polynomial Basis MultiplicationJournal of Hardware and Systems Security10.1007/s41635-019-00087-5Online publication date: 2-Jan-2020
https://doi.org/10.1007/s41635-019-00087-5
Long JKu JMemik SIsmail Y(2018)SACTAIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202399218:9(1323-1336)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2009.2023992
Uslu BErdem S(2018)Versatile digit serial multipliers for binary extension fieldsComputers and Electrical Engineering10.1016/j.compeleceng.2015.07.00646:C(29-45)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1016/j.compeleceng.2015.07.006
Ibrahim AGebali F(2018)Low Power Semi-systolic Architectures for Polynomial-Basis Multiplication over GF(2m) Using Progressive Multiplier ReductionJournal of Signal Processing Systems10.1007/s11265-015-1000-x82:3(331-343)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1007/s11265-015-1000-x
Rashidi BRezaeian Farashahi RSayedi S(2017) High‐performance and high‐speed implementation of polynomial basis Itoh–Tsujii inversion algorithm over GF(2 m ) IET Information Security10.1049/iet-ifs.2015.046111:2(66-77)Online publication date: Mar-2017
https://doi.org/10.1049/iet-ifs.2015.0461
Rashidi BSayedi SFarashahi R(2016)High-speed hardware architecture of scalar multiplication for binary elliptic curve cryptosystemsMicroelectronics Journal10.1016/j.mejo.2016.03.00652:C(49-65)Online publication date: 1-Jun-2016
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Pamula DHrynkiewicz E(2013)Area-speed efficient modular architecture for GF(2^m) multipliers dedicated for cryptographic applications2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)10.1109/DDECS.2013.6549784(30-35)Online publication date: Apr-2013
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Zhang JSong ZHu Q(2012)A Systolic Bit-Parallel Multiplier with Flexible Latency and Complexity over GF(2m) Using Polynomial BasisAdvanced Materials Research10.4028/www.scientific.net/AMR.457-458.848457-458(848-855)Online publication date: Jan-2012
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Chen LChang PChang YLee C(2012)A Scalable Architecture for Dual Basis GF(2m) MultiplicationsProceedings of the 2012 International Symposium on Biometrics and Security Technologies10.1109/ISBAST.2012.13(45-50)Online publication date: 26-Mar-2012
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Super Digit-Serial Systolic Multiplier over GF(2^m)

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Super Digit-Serial Systolic Multiplier over GF(2^m)

Bit-Serial Systolic Divider and Multiplier for Finite Fields GF(2/sup m/)

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A digit-serial multiplier for finite field GF(2^m)