Article

Towards formal probabilistic power-performance design space exploration

Authors:

Michael OrshanskyAuthors Info & Claims

GLSVLSI '06: Proceedings of the 16th ACM Great Lakes symposium on VLSI

Pages 229 - 234

https://doi.org/10.1145/1127908.1127962

Published: 30 April 2006 Publication History

Abstract

We describe a formal probabilistic power-performance design space exploration technique. The technique aims at enabling hierarchical design space exploration based on a fully probabilistic description of power-performance tradeoffs. Probabilistic Pareto sets in power-performance space are proposed as canonical encodings of the power and delay tradeoffs in designs under any source of uncertainty. An algorithm to compute a composite probabilistic power-performance Pareto set for series or parallel connections of circuit blocks is also developed and validated. The algorithm is based on numerical convolution and is suitable for micro-architecture pipeline design exploration in the presence of process variability.

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Cited By

Singh ADziurzanski PMendis HIndrusiak L(2017)A Survey and Comparative Study of Hard and Soft Real-Time Dynamic Resource Allocation Strategies for Multi-/Many-Core SystemsACM Computing Surveys10.1145/305726750:2(1-40)Online publication date: 11-Apr-2017
https://dl.acm.org/doi/10.1145/3057267
Singh AShafique MKumar AHenkel J(2016)Resource and Throughput Aware Execution Trace Analysis for Efficient Run-Time Mapping on MPSoCsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.244693835:1(72-85)Online publication date: Jan-2016
https://doi.org/10.1109/TCAD.2015.2446938
Singh ADas AKumar A(2013)RAPIDITASProceedings of the 2013 Euromicro Conference on Digital System Design10.1109/DSD.2013.93(836-843)Online publication date: 4-Sep-2013
https://dl.acm.org/doi/10.1109/DSD.2013.93
Show More Cited By

Index Terms

Towards formal probabilistic power-performance design space exploration
1. Computer systems organization
2. Hardware
  1. Hardware validation

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Published In

cover image ACM Conferences

GLSVLSI '06: Proceedings of the 16th ACM Great Lakes symposium on VLSI

April 2006

450 pages

ISBN:1595933476

DOI:10.1145/1127908

General Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University
,
Program Chairs:
Vijaykrishnan Narayanan
Pennsylvania State University
,
Hai Zhou
Northwestern University

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 30 April 2006

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GLSVLSI06

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GLSVLSI06: Great Lakes Symposium on VLSI 2006

April 30 - May 1, 2006

PA, Philadelphia, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Singh ADziurzanski PMendis HIndrusiak L(2017)A Survey and Comparative Study of Hard and Soft Real-Time Dynamic Resource Allocation Strategies for Multi-/Many-Core SystemsACM Computing Surveys10.1145/305726750:2(1-40)Online publication date: 11-Apr-2017
https://dl.acm.org/doi/10.1145/3057267
Singh AShafique MKumar AHenkel J(2016)Resource and Throughput Aware Execution Trace Analysis for Efficient Run-Time Mapping on MPSoCsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.244693835:1(72-85)Online publication date: Jan-2016
https://doi.org/10.1109/TCAD.2015.2446938
Singh ADas AKumar A(2013)RAPIDITASProceedings of the 2013 Euromicro Conference on Digital System Design10.1109/DSD.2013.93(836-843)Online publication date: 4-Sep-2013
https://dl.acm.org/doi/10.1109/DSD.2013.93
Piscitelli RPimentel ARosenstiel WMacii E(2012)Design space pruning through hybrid analysis in system-level design space explorationProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492902(781-786)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492902
Piscitelli RPimentel A(2012)Interleaving methods for hybrid system-level MPSoC design space exploration2012 International Conference on Embedded Computer Systems (SAMOS)10.1109/SAMOS.2012.6404152(7-14)Online publication date: Jul-2012
https://doi.org/10.1109/SAMOS.2012.6404152
Piscitelli RPimentel A(2012)Design space pruning through hybrid analysis in system-level design space exploration2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.1109/DATE.2012.6176600(781-786)Online publication date: Mar-2012
https://doi.org/10.1109/DATE.2012.6176600

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