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On dependability of FPGA-based evolvable hardware systems that utilize virtual reconfigurable circuits

Published: 03 May 2006 Publication History
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  • Abstract

    This paper describes experiments conducted to estimate how the use of (area-demanding) virtual reconfigurable circuits (VRC) influences the dependability of FPGA-based evolvable systems. It is shown that these systems are not so sensitive to faults as their area-demanding implementations could evoke. Evolutionary techniques are utilized to design fault tolerant circuits in a virtual reconfigurable circuit and to perform their automatic functional recovery in case of occurence of faults in a configuration memory of FPGA. All the experiments are performed on models of reconfigurable devices. This paper does not claim that the use of the VRC improves the dependability; it shows how the use of VRCs could influence the dependability.

    References

    [1]
    M. Alderighi, A. Candelori, F. Casini, S. D'Angelo, M. Mancini, A. Paccagnella, S. Pastore, and G.R. Sechi. Heavy Ion Effects on Configuration Logic of Virtex FPGAs. InProc. of 11th IEEE International On-Line Testing Symposium, pages 49--53, Los Alamitos, CA, USA, 2005. IEEE Computer Society.
    [2]
    P. Bernardi, M. Sonza Reorda, L. Sterpone, and M. Violante. On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs. InProc. of 10th IEEE International On-Line Testing Symposium, pages 115--120, Los Alamitos, CA, USA, 2004. IEEE Computer Society.
    [3]
    D. Bradley, C. Ortega-Sanchez, and A. Tyrrell. Embryonics + Immunotronics: A Bio-Inspired Approach to Fault Tolerance. InProc. of the 2nd NASA/DoD Workshop on Evolvable Hardware, pages 215--222, Los Alamitos, CA, USA, 2000. IEEE Computer Society.
    [4]
    C. Carmichael, M. Caffrey, and A. Salazar. Correcting Single-Event Upsets Through Virtex Partial Configuration. Xilinx Application Note XAPP 216, 2000.
    [5]
    M. Garvie and A. Thompson. Evolution of Self-diagnosing Hardware. InProc. of the 5th Int. Conf. on Evolvable Systems: From Biology to Hardware ICES'03, volume 2606 ofLecture Notes in ComputerScience, pages 238--248, Trondheim, Norway, 2003. Springer-Verlag.
    [6]
    K. Glette and J. Torresen. A Flexible On-chip Evolution System Implemented on a Xilinx Virtex-II Pro Device. InProc. of the 6th Int. Conf. on Evolvable Systems: From Biology to Hardware ICES'05, volume 3637 ofLecture Notes in Computer Science, pages 66--75, Sitges, Spain, 2005. Springer-Verlag.
    [7]
    J. Kořenek and L. Sekanina. Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs. InProc. of the 6th Int. Conf. on Evolvable Systems: From Biology to Hardware ICES'05, volume 3637 ofLecture Notes in Computer Science, pages 46--55, Sitges, Spain, 2005. Springer-Verlag.
    [8]
    J. Lohn, G. Larchev, and R. DeMara. A Genetic Representation for Evolutionary Fault Recovery in Virtex FPGAs. InProc. of the 5th Int. Conf. on Evolvable Systems: From Biology to Hardware ICES'03, volume 2606 ofLecture Notes in Computer Science, pages 47--56, Trondheim, Norway, 2003. Springer-Verlag.
    [9]
    D. Mange, M. Sipper, A. Stauffer, and G. Tempesti. Towards Robust Integrated Circuits: The Embryonics Approach. Proceedings of IEEE, 88(4):516--541, 2000.
    [10]
    T. Martínek and L. Sekanina. An Evolvable Image Filter: Experimental Evaluation of a Complete Hardware Implementation in FPGA. InProc. of the 6th Int. Conf. on Evolvable Systems: From Biology to Hardware ICES'05, volume 3637 ofLecture Notes in Computer Science, pages 76--85, Sitges, Spain, 2005. Springer-Verlag.
    [11]
    J. Masner, J. Cavalieri, J. Frenzel, and J. Foster. Size versus robustness in evolved sorting networks: Is bigger better? InThe Second NASA/DoD workshop on Evolvable Hardware, pages 81--87, Palo Alto, California, 2000. IEEE Computer Society.
    [12]
    J. Miller, D. Job, and V. Vassilev. Principles in the Evolutionary Design of Digital Circuits -- Part I. Genetic Programming and Evolvable Machines, 1(1):8--35, 2000.
    [13]
    J. F. Miller and M. Hartmann. Evolving messy gates for fault tolerance: Some preliminary findings. InThe Third NASA/DoD workshop on Evolvable Hardware, pages 116--123, Long Beach, California, 2001. IEEE Computer Society.
    [14]
    D. K. Pradhan. Fault-Tolerant Computer System Design. Prentice Hall, 1996.
    [15]
    Qpro virtex 2.5v qml high-reliability fpgas, xilinx data sheet, 2001.
    [16]
    L. Sekanina. Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware. InProc. of the 5th Int. Conf. on Evolvable Systems: From Biology to Hardware ICES'03, volume 2606 ofLecture Notes in Computer Science, pages 186--197, Trondheim, 2003. Springer-Verlag.
    [17]
    L. Sekanina. Evolvable Components: From Theory to Hardware Implementations. Natural Computing Series, Springer Verlag, 2004.
    [18]
    L. Sekanina and S. Friedl. An Evolvable Combinational Unit for FPGAs. Computing and Informatics, 23(5):461--486, 2004.
    [19]
    L. Sekanina and T. Martinek and Z. Gajda.Extrinsic and Intrinsic Evolution of Multifunctional Combinational Modules. InIEEE Congress on Evolutionary Computation, 2006, submitted.
    [20]
    A. Stoica, D. Keymeulen, T. Arslan, V. Duong, R. Zebulum, I. Ferguson, and X. Guo. Circuit Self-Recovery Experiments in Extreme Environments. InProc. of the 2004 NASA/DoD Conference on Evolvable Hardware, pages 142--145, Seattle, USA, 2004. IEEE Computer Society.
    [21]
    A. Stoica, D. Keymeulen, A. Thakoor, T. Daud, G. Klimech, Y. Jin, R. Tawel, andV. Duong. Evolution of Analog Circuits on Field Programmable Transistor Arrays. InProc. of the 2000 NASA/DoD Conference on Evolvable Hardware, pages 99--108, Palo Alta, CA, 2000. IEEE Computer Society.
    [22]
    A. Stoica, D. Keymeulen, and R. Zebulum. Evolvable hardware solutions for extreme temperature electronics. InThe Third NASA/DoD workshop on Evolvable Hardware, pages 93--97, Long Beach, CA, 2001. IEEE Computer Society.
    [23]
    A. Thompson. Hardware Evolution: Automatic Design of Electronic Circuits in Reconfigurable Hardware by Artificial Evolution. Springer Verlag, London, 1998.
    [24]
    M. Wirthlin, E. Johnson, N. Rollins, M. Caffrey, and P. Graham. The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets. InProc. of the 11th Symposium on FPGA-Based Custom Computing Machines FCCM'03, pages 133--142. IEEE CS, 2003.
    [25]
    R. Zebulum, D. Keymeulen, V. Duong, X. Guo, M. I. Ferguson, and A. Stoica. Experimental Results in Evolutionary Fault-Recovery for Field Programmable Analog Devices. InProc. of the 2003 NASA/DoD Conference on Evolvable Hardware, pages 182--186, Chicago, USA, 2003. IEEE Computer Society.
    [26]
    Y. Zhang, S. Smith, and A. Tyrrell. Digital Circuit Design Using Intrinsic Evolvable Hardware.InProc. of the 2004 NASA/DoD Conference on Evolvable Hardware, pages 55--62, Seattle, USA, 2004. IEEE Computer Society.

    Cited By

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    • (2018)Evolutionary Fault Tolerance Method Based on Virtual Reconfigurable Circuit With Neural Network ArchitectureIEEE Transactions on Evolutionary Computation10.1109/TEVC.2017.277987422:6(949-960)Online publication date: Dec-2018
    • (2017)Intelligent Fault‐Tolerance TechniquesFault‐Tolerance Techniques for Spacecraft Control Computers10.1002/9781119107392.ch8(261-336)Online publication date: 27-Jan-2017
    • (2007)An intrinsic evolvable hardware based on multiplexer module arrayProceedings of the 7th international conference on Evolvable systems: from biology to hardware10.5555/1792161.1792166(35-44)Online publication date: 21-Sep-2007
    • Show More Cited By

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    1. On dependability of FPGA-based evolvable hardware systems that utilize virtual reconfigurable circuits

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          cover image ACM Conferences
          CF '06: Proceedings of the 3rd conference on Computing frontiers
          May 2006
          430 pages
          ISBN:1595933026
          DOI:10.1145/1128022
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          Published: 03 May 2006

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          Author Tags

          1. FPGA
          2. dependability
          3. evolutionary algorithms
          4. evolvable hardware

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          CF06: Computing Frontiers Conference
          May 3 - 5, 2006
          Ischia, Italy

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          Overall Acceptance Rate 273 of 785 submissions, 35%

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          Cited By

          View all
          • (2018)Evolutionary Fault Tolerance Method Based on Virtual Reconfigurable Circuit With Neural Network ArchitectureIEEE Transactions on Evolutionary Computation10.1109/TEVC.2017.277987422:6(949-960)Online publication date: Dec-2018
          • (2017)Intelligent Fault‐Tolerance TechniquesFault‐Tolerance Techniques for Spacecraft Control Computers10.1002/9781119107392.ch8(261-336)Online publication date: 27-Jan-2017
          • (2007)An intrinsic evolvable hardware based on multiplexer module arrayProceedings of the 7th international conference on Evolvable systems: from biology to hardware10.5555/1792161.1792166(35-44)Online publication date: 21-Sep-2007
          • (2007)Evolutionary functional recovery in virtual reconfigurable circuitsACM Journal on Emerging Technologies in Computing Systems10.1145/1265949.12659543:2(8-es)Online publication date: 1-Jul-2007
          • (2007)Evolving virtual reconfigurable circuit for a fault tolerant system2007 IEEE Congress on Evolutionary Computation10.1109/CEC.2007.4424658(1555-1561)Online publication date: Sep-2007

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