Article

State encoding of large asynchronous controllers

Authors:

Jordi CortadellaAuthors Info & Claims

DAC '06: Proceedings of the 43rd annual Design Automation Conference

Pages 939 - 944

https://doi.org/10.1145/1146909.1147148

Published: 24 July 2006 Publication History

Abstract

A novel method to solve the state encoding problem in Signal Transition Graphs is presented. It is based on the structural theory of Petri nets and can be applied to large specifications with hundreds of signals. This new method opens the door to incorporate logic synthesis in the design flow of large control circuits obtained from high-level specifications. The experimental results validate the quality of the encoded circuits and show the significant improvements that can be obtained by the synthesis of large controllers.

References

[1]

K. v. Berkel. Handshake Circuits: an Asynchronous Architecture for VLSI Programming, volume 5 of International Series on Parallel Computation. Cambridge University Press, 1993.

Digital Library

[2]

J. Carmona and J. Cortadella. ILP models for the synthesis of asynchronous control circuits. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 818--826, Nov. 2003.

Digital Library

[3]

T. Chelcea, A. Bardsley, D. Edwards, and S. M. Nowick. A burst-mode oriented back-end for the Balsa synthesis system. In Proc. Design, Automation and Test in Europe (DATE), pages 330--337, Mar. 2002.

Digital Library

[4]

J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev. A region-based theory for state assignment in speed-independent circuits. IEEE Transactions on Computer-Aided Design, 16(8):793--812, Aug. 1997.

Digital Library

[5]

J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev. Logic Synthesis of Asynchronous Controllers and Interfaces. Springer-Verlag, 2002.

Digital Library

[6]

J. Desel and J. Esparza. Reachability in cyclic extended free-choice systems. TCS 114, Elsevier Science Publishers B.V., 1993.

Digital Library

[7]

D. Edwards and A. Bardsley. Balsa: An asynchronous hardware synthesis language. The Computer Journal, 45(1):12--18, 2002.

[8]

R. M. Fuhrer, B. Lin, and S. M. Nowick. Symbolic hazard-free minimization and encoding of asynchronous finite state machines. In Proc. International Conf. Computer-Aided Design (ICCAD). IEEE Computer Society Press, 1995.

Digital Library

[9]

F. García-Vallés and J. M. Colom. Structural analysis of signal transition graphs. In D. H. I. B. Farwer and M. Stehr, editors, Proceedings of the Workshop Petri Nets in System Engineering (PNSE'97). Modelling, Verification and Validation, pages 123--134, 1997.

[10]

V. Khomenko, M. Koutny, and A. Yakovlev. Detecting state coding conflicts in STG unfoldings using SAT. In Int. Conf. on Application of Concurrency to System Design, June 2003.

Digital Library

[11]

K.-J. Lin, J.-W. Kuo, and C.-S. Lin. Direct synthesis of hazard-free asynchronous circuits from STGs based on lock relation and MG-decomposition approach. In Proc. European Design and Test Conference, pages 178--183. IEEE Computer Society Press, 1994.

[12]

T. Murata. Petri nets: Properties, analysis and applications. Proceedings of the IEEE, 77(4):541--574, Apr. 1989.

[13]

E. Pastor and J. Cortadella. An efficient unique state coding algorithm for signal transition graphs. In Proc. International Conf. Computer Design (ICCD), pages 174--177, Oct. 1993.

[14]

M. Silva, E. Teruel, and J. M. Colom. Linear algebraic and linear programming techniques for the analysis of place/transition net systems. In Reisig, W. and Rozenberg, G., editors, Lecture Notes in Computer Science: Lectures on Petri Nets I: Basic Models, volume 1491, pages 309--373. Springer-Verlag, 1998.

Digital Library

[15]

P. Vanbekbergen. Synthesis of Asynchronous Control Circuits from Graph-Theoretic Specifications. PhD thesis, Catholic University of Leuven, Sept. 1993.

Cited By

Khomenko VSchaefer MVogler W(2019)Output-Determinacy and Asynchronous Circuit SynthesisFundamenta Informaticae10.5555/2366276.236628288:4(541-579)Online publication date: 4-Jan-2019
https://dl.acm.org/doi/10.5555/2366276.2366282
Khomenko VMadalinski AYakovlev A(2019)Resolution of Encoding Conflicts by Signal Insertion and Concurrency Reduction Based on STG UnfoldingsFundamenta Informaticae10.5555/2366076.236608086:3(299-323)Online publication date: 4-Jan-2019
https://dl.acm.org/doi/10.5555/2366076.2366080
Khomenko VSchaefer MVogler W(2019)Output-Determinacy and Asynchronous Circuit SynthesisFundamenta Informaticae10.5555/1497088.149709488:4(541-579)Online publication date: 4-Jan-2019
https://dl.acm.org/doi/10.5555/1497088.1497094
Show More Cited By

Index Terms

State encoding of large asynchronous controllers
1. Applied computing
  1. Physical sciences and engineering
    1. Engineering
2. Hardware
  1. Integrated circuits
    1. Logic circuits

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Published In

cover image ACM Conferences

DAC '06: Proceedings of the 43rd annual Design Automation Conference

July 2006

1166 pages

ISBN:1595933816

DOI:10.1145/1146909

General Chair:
Ellen M. Sentovich
Cadence Berkeley Labs, Berkeley, CA

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 24 July 2006

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DAC06

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DAC06: The 43rd Annual Design Automation Conference 2006

July 24 - 28, 2006

CA, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Citations

Cited By

Khomenko VSchaefer MVogler W(2019)Output-Determinacy and Asynchronous Circuit SynthesisFundamenta Informaticae10.5555/2366276.236628288:4(541-579)Online publication date: 4-Jan-2019
https://dl.acm.org/doi/10.5555/2366276.2366282
Khomenko VMadalinski AYakovlev A(2019)Resolution of Encoding Conflicts by Signal Insertion and Concurrency Reduction Based on STG UnfoldingsFundamenta Informaticae10.5555/2366076.236608086:3(299-323)Online publication date: 4-Jan-2019
https://dl.acm.org/doi/10.5555/2366076.2366080
Khomenko VSchaefer MVogler W(2019)Output-Determinacy and Asynchronous Circuit SynthesisFundamenta Informaticae10.5555/1497088.149709488:4(541-579)Online publication date: 4-Jan-2019
https://dl.acm.org/doi/10.5555/1497088.1497094
Khomenko VMadalinski AYakovlev A(2019)Resolution of Encoding Conflicts by Signal Insertion and Concurrency Reduction Based on STG UnfoldingsFundamenta Informaticae10.5555/1487698.148770286:3(299-323)Online publication date: 4-Jan-2019
https://dl.acm.org/doi/10.5555/1487698.1487702
Khomenko VSchaefer MVogler WWollowski R(2019)STG decomposition strategies in combination with unfoldingActa Informatica10.1007/s00236-009-0102-y46:6(433-474)Online publication date: 2-Jan-2019
https://dl.acm.org/doi/10.1007/s00236-009-0102-y
Wisniewski RKaratkevich AAdamski MCosta AGomes L(2018)Prototyping of Concurrent Control Systems With Application of Petri Nets and Comparability GraphsIEEE Transactions on Control Systems Technology10.1109/TCST.2017.269220426:2(575-586)Online publication date: Mar-2018
https://doi.org/10.1109/TCST.2017.2692204
Grobelna IWisniewski RGrobelny MWisniewska M(2017)Design and Verification of Real-Life Processes With Application of Petri NetsIEEE Transactions on Systems, Man, and Cybernetics: Systems10.1109/TSMC.2016.253167347:11(2856-2869)Online publication date: Nov-2017
https://doi.org/10.1109/TSMC.2016.2531673
Wiśniewski RWiśniewski R(2016)Decomposition of Concurrent Control SystemsPrototyping of Concurrent Control Systems Implemented in FPGA Devices10.1007/978-3-319-45811-3_6(77-98)Online publication date: 1-Oct-2016
https://doi.org/10.1007/978-3-319-45811-3_6
Wiśniewski RWiśniewski R(2016)IntroductionPrototyping of Concurrent Control Systems Implemented in FPGA Devices10.1007/978-3-319-45811-3_1(1-13)Online publication date: 1-Oct-2016
https://doi.org/10.1007/978-3-319-45811-3_1
Grobelna IWisniewska MWisniewski RGrobelny MMroz P(2014)Decomposition, validation and documentation of control process specification in form of a Petri net2014 7th International Conference on Human System Interactions (HSI)10.1109/HSI.2014.6860481(232-237)Online publication date: Jun-2014
https://doi.org/10.1109/HSI.2014.6860481
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