Lookup table based simulation and statistical modeling of Sigma-Delta ADCs

Sigma-Delta (ΕΔ) ADCs have been widely adopted in data conversion applications due to the good performance. However, oversampling and complex circuit behavior render the simulation of these designs prohibitively time consuming. In this paper, a lookup table (LUT) based modeling technique is presented for efficient analysis of ΕΔ ADCs. In the proposed approach, various transistor-level circuit non-idealities are systematically characterized at the building-block level and the complete ADC is simulated much more efficiently using these table models. As such, our approach can provide up to four orders of magnitude runtime speedup over SPICE-like simulators, hence significantly shortening the CPU time required for evaluating system performances such as SNDR (signal-noise-distortion-ratio). The proposed LUT modeling technique is further extended to assess performance variations due to parameter fluctuations. The resulting parameterized LUT modeling technique not only facilitates scalable performance variation analysis of complex ΕΔ ADC designs, but also allows us to feasibly extract statistical performance correlation models for low-cost test solutions.