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Ant colony based routing architecture for minimizing hot spots in NOCs

Published: 28 August 2006 Publication History

Abstract

In this paper, a routing model for minimizing hot spots in the network on chip (NOC) is presented. The model makes use of AntNet routing algorithm which is based on Ant colony. Using this algorithm, which we call AntNet routing algorithm, heavy packet traffics are distributed on the chip minimizing the occurrence of hot spots. To evaluate the efficiency of the scheme, the proposed algorithm was compared to the XY, Odd-Even, and DyAD routing models. The simulation results show that in realistic (Transpose) traffic as well as in heavy packet traffic, the proposed model has less average delay and peak power compared to the other routing models. In addition, the maximum temperature in the proposed algorithm is less than those of the other routing algorithms.

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Cited By

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  • (2012)Networks on chips: structure and design methodologiesJournal of Electrical and Computer Engineering10.1155/2012/5094652012(2-2)Online publication date: 1-Jan-2012
  • (2012)Optimized Q-learning model for distributing traffic in on-Chip NetworksProceedings of the 2012 IEEE 3rd International Conference on Networked Embedded Systems for Every Application (NESEA)10.1109/NESEA.2012.6474016(1-8)Online publication date: 13-Dec-2012
  • (2011)PreliminariesReconfigurable Networks-on-Chip10.1007/978-1-4419-9341-0_2(15-31)Online publication date: 15-Dec-2011
  • Show More Cited By

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    cover image ACM Conferences
    SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design
    August 2006
    248 pages
    ISBN:1595934790
    DOI:10.1145/1150343
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 28 August 2006

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    Author Tags

    1. dynamic routing algorithm
    2. network on chip

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    SBCCI06: 19th Symposium on Integrated Circuits and System Design
    August 28 - September 1, 2006
    MG, Ouro Preto, Brazil

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    Cited By

    View all
    • (2012)Networks on chips: structure and design methodologiesJournal of Electrical and Computer Engineering10.1155/2012/5094652012(2-2)Online publication date: 1-Jan-2012
    • (2012)Optimized Q-learning model for distributing traffic in on-Chip NetworksProceedings of the 2012 IEEE 3rd International Conference on Networked Embedded Systems for Every Application (NESEA)10.1109/NESEA.2012.6474016(1-8)Online publication date: 13-Dec-2012
    • (2011)PreliminariesReconfigurable Networks-on-Chip10.1007/978-1-4419-9341-0_2(15-31)Online publication date: 15-Dec-2011
    • (2008)Fluidity concept for NoC: A congestion avoidance and relief routing scheme2008 IEEE International SOC Conference10.1109/SOCC.2008.4641481(65-70)Online publication date: Sep-2008
    • (2008)Flow Maximization for NoC Routing AlgorithmsProceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2008.52(335-340)Online publication date: 7-Apr-2008

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