Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1145/1152154.1152170acmconferencesArticle/Chapter ViewAbstractPublication PagespactConference Proceedingsconference-collections
Article

Efficient data protection for distributed shared memory multiprocessors

Published: 16 September 2006 Publication History
  • Get Citation Alerts
  • Abstract

    Data security in computer systems has recently become an increasing concern, and hardware-based attacks have emerged. As a result, researchers have investigated hardware encryption and authentication mechanisms as a means of addressing this security concern. Unfortunately, no such techniques have been investigated for Distributed Shared Memory (DSM) multiprocessors, and previously proposed techniques for uni-processor and Symmetric Multiprocessor (SMP) systems cannot be directly used for DSMs. This work is the first to examine the issues involved in protecting secrecy and integrity of data in DSM systems. We first derive security requirements for processor-processor communication in DSMs, and find that different types of coherence messages need different protection. Then we propose and evaluate techniques to provide efficient encryption and authentication of the data in DSM systems. Our simulation results using SPLASH-2 benchmarks show that the execution time overhead for our three proposed approaches is small and ranges from 6% to 8% on a 16-processor DSM system, relative to a similar DSM without support for data secrecy and integrity.

    References

    [1]
    AMD. AMD Opteron Processor for Servers and Workstations. http://www.amd.com/us-en/Processors/ ProductInformation/0,30 8796 8804,00.html, 2005.
    [2]
    R. Anderson. Why cryptosystems fail. In Proceedings of the 1st Conf. Computer and Communications Security (CCS '93), pages 215--227, 1993.
    [3]
    R. K. B. Yang, S. Mishra. A high speed architecture for galois/counter mode of operation (gcm). In Cryptology ePrint Archive: Report 2005/146, 2005.
    [4]
    D. Bartholomew. On Demand Computing - IT On Tap? http://www.industryweek.com/ReadArticle.aspx? ArticleID=10303&SectionID=4, June 2005.
    [5]
    B. Gassend, G. Suh, D. Clarke, M. Dijk, and S. Devadas. Caches and Hash Trees for Efficient Memory Integrity Verification. In Proc of the 9th International Symposium on High Performance Computer Architecture (HPCA-9), 2003.
    [6]
    T. Gilmont, J.-D. Legat, and J.-J. Quisquater. Enhancing the Security in the Memory Management Unit. In Proc. of the 25th EuroMicro Conference, 1999.
    [7]
    A. Huang. Hacking the Xbox: An Introduction to Reverse Engineering. No Starch Press, San Francisco, CA, 2003.
    [8]
    A. B. Huang. The Trusted PC: Skin-Deep Security. IEEE Computer, 35(10):103--105, 2002.
    [9]
    IBM. IBM Power4 System Architecture White Paper. http://www-1.ibm.com/servers/eserver/pseries/ hardware/whitepapers/power4.html, 2002.
    [10]
    J. Renau, et al. SESC. http://sesc.sourceforge.net, 2004.
    [11]
    T. Kgil, L. Falk, and T. Mudge. ChipLock: Support for Secure Microarchitectures. In Proceedings of the Workshop on Architectural Support for Security and Anti-Virus (WASSA), Oct. 2004.
    [12]
    D. Lie, J. Mitchell, C. Thekkath, and M. Horowitz. Specifying and Verifying Hardware for Tamper- Resistant Software. In IEEE Symposium on Security and Privacy, 2003.
    [13]
    D. Lie, C. Thekkath, M. Mitchell, P. Lincoln, D. Boneh, J. MItchell, and M. Horowitz. Architectural Support for Copy and Tamper Resistant Software. In Proc. of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, 2000.
    [14]
    D. A. McGrew and J. Viega. The Galois/Counter Mode of Operation (GCM). http://csrc.nist.gov/ CryptoToolkit/modes/proposedmodes/gcm/, 2004.
    [15]
    T. Olavsrud. HP Issues Battle Cry in High-End Unix Server Market. ServerWatch, http://www.serverwatch.com/news/article.php/1399451, 2000.
    [16]
    W. Shi, H.-H. Lee, M. Ghosh, and C. Lu. Architectural Support for High Speed Protection of Memory Integrity and Confidentiality in Multiprocessor Systems. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, pages 123--134, September 2004.
    [17]
    W. Shi, H.-H. Lee, M. Ghosh, C. Lu, and A. Boldyreva. High Efficiency Counter Mode Security Architecture via Prediction and Precomputation. In Proceedings of the 32nd International Symposium on Computer Architecture, June 2005.
    [18]
    W. Shi, H.-H. Lee, C. Lu, and M. Ghosh. Towards the Issues in Architectural Support for Protection of Software Execution. In Proceedings of the Workshop on Architectureal Support for Security and Anti-virus, pages 1--10, October 2004.
    [19]
    P. Shivakumar and N. P. Jouppi. Cacti 3.0: An integrated cache timing, power, and area model. In Technical Report WRL Technical Report 2001/2. Compaq Western Research Laboratory, Aug 2001.
    [20]
    Silicon Graphics, Inc. SGI Altix 3000 Data Sheet. http://www.sgi.com/products/servers/altix, 2004.
    [21]
    G. Suh, D. Clarke, B. Gassend, M. van Dijk, and S. Devadas. Efficient Memory Integrity Verification and Encryption for Secure Processor. In Proc. of the 36th Annual International Symposium on Microarchitecture, 2003.
    [22]
    S. Woo, M. Ohara, E. Torrie, J. Singh, and A. Gupta. The splash-2 programs: characterization and methodological considerations. In Proceedings of the 22nd International Symposium on Computer Architecture, pages 24--36, 1995.
    [23]
    C. Yan, B. Rogers, D. Englender, Y. Solihin, and M. Prvulovic. Improving cost, performance, and security of memory encryption and authentication. In Proc. of the International Symposium on Computer Architecture, 2006.
    [24]
    J. Yang, Y. Zhang, and L. Gao. Fast Secure Processor for Inhibiting Software Piracy and Tampering. In Proc. of the 36th Annual International Symposium on Microarchitecture, 2003.
    [25]
    Y. Zhang, L. Gao, J. Yang, X. Zhang, and R. Gupta. SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors. In International Symposium on High-Performance Computer Architecture, February 2005.

    Cited By

    View all
    • (2024)Supporting Secure Multi-GPU Computing with Dynamic and Batched Metadata Management2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00025(204-217)Online publication date: 2-Mar-2024
    • (2023)Efficient Distributed Secure Memory with Migratable Merkle Tree2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071130(347-360)Online publication date: Feb-2023
    • (2023)SecPB: Architectures for Secure Non-Volatile Memory with Battery-Backed Persist Buffers2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071082(677-690)Online publication date: Feb-2023
    • Show More Cited By

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    PACT '06: Proceedings of the 15th international conference on Parallel architectures and compilation techniques
    September 2006
    308 pages
    ISBN:159593264X
    DOI:10.1145/1152154
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 16 September 2006

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. DSM multiprocessor
    2. data security
    3. memory encryption and authentication

    Qualifiers

    • Article

    Conference

    PACT06
    Sponsor:

    Acceptance Rates

    Overall Acceptance Rate 121 of 471 submissions, 26%

    Upcoming Conference

    PACT '24

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)49
    • Downloads (Last 6 weeks)3
    Reflects downloads up to 10 Aug 2024

    Other Metrics

    Citations

    Cited By

    View all
    • (2024)Supporting Secure Multi-GPU Computing with Dynamic and Batched Metadata Management2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00025(204-217)Online publication date: 2-Mar-2024
    • (2023)Efficient Distributed Secure Memory with Migratable Merkle Tree2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071130(347-360)Online publication date: Feb-2023
    • (2023)SecPB: Architectures for Secure Non-Volatile Memory with Battery-Backed Persist Buffers2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071082(677-690)Online publication date: Feb-2023
    • (2023)OMT: A Run-time Adaptive Architectural Framework for Bonsai Merkle Tree-Based Secure Authentication with Embedded Heterogeneous Memory2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)10.1109/HOST55118.2023.10133074(191-202)Online publication date: 1-May-2023
    • (2021)Bonsai Merkle Forests: Efficiently Achieving Crash Consistency in Secure Persistent MemoryMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480067(1227-1240)Online publication date: 18-Oct-2021
    • (2021)Performance-Enhanced Integrity Verification for Large Memories2021 International Symposium on Secure and Private Execution Environment Design (SEED)10.1109/SEED51797.2021.00016(50-62)Online publication date: Sep-2021
    • (2020)Persist Level Parallelism: Streamlining Integrity Tree Updates for Secure Persistent Memory2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO50266.2020.00015(14-27)Online publication date: Oct-2020
    • (2019)Triad-NVMProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322250(104-115)Online publication date: 22-Jun-2019
    • (2019)Architectural Support for Containment-based SecurityProceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3297858.3304020(361-377)Online publication date: 4-Apr-2019
    • (2018)Principles of Secure Processor Architecture DesignSynthesis Lectures on Computer Architecture10.2200/S00864ED1V01Y201807CAC04513:3(1-173)Online publication date: 18-Oct-2018
    • Show More Cited By

    View Options

    Get Access

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media