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Towards a visual notation for pipelining in a visual programming language for programming FPGAs

Published: 06 July 2006 Publication History

Abstract

VERTIPH is a visual language designed to aid in the development of image processing algorithms on FPGAs (Field Programmable Gate Arrays). We justify the use of a visual language for this purpose, and describe the key parts of VERTIPH. One aspect of importance is how to clearly and efficiently represent a pipeline of processors, and in particular distinguish a pipeline from the simpler serial or parallel structures. This paper develops a number of pipeline representations, discussing the rationale behind and limitations associated with each representation. The culmination of this development is the Sequential Pipeline with Detailed Bars, visually an efficient and unambiguous representation.

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Cited By

View all
  • (2023)Design ConstraintsDesign for Embedded Image Processing on FPGAs10.1002/9781119819820.ch4(77-104)Online publication date: 5-Sep-2023
  • (2023)Design ProcessDesign for Embedded Image Processing on FPGAs10.1002/9781119819820.ch3(45-76)Online publication date: 5-Sep-2023
  • (2022)Domain-Specific Visual Language for Data Engineering QualityProceedings of the 1st ACM SIGPLAN International Workshop on Programming Abstractions and Interactive Notations, Tools, and Environments10.1145/3563836.3568727(48-56)Online publication date: 29-Nov-2022
  • Show More Cited By

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cover image ACM Other conferences
CHINZ '06: Proceedings of the 7th ACM SIGCHI New Zealand chapter's international conference on Computer-human interaction: design centered HCI
July 2006
139 pages
ISBN:1595934731
DOI:10.1145/1152760
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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  • New Zealand Chapter of ACM SIGCHI
  • The University of Canterbury

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 July 2006

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Author Tags

  1. FPGA
  2. pipelining
  3. visual programming language

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Overall Acceptance Rate 8 of 23 submissions, 35%

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Cited By

View all
  • (2023)Design ConstraintsDesign for Embedded Image Processing on FPGAs10.1002/9781119819820.ch4(77-104)Online publication date: 5-Sep-2023
  • (2023)Design ProcessDesign for Embedded Image Processing on FPGAs10.1002/9781119819820.ch3(45-76)Online publication date: 5-Sep-2023
  • (2022)Domain-Specific Visual Language for Data Engineering QualityProceedings of the 1st ACM SIGPLAN International Workshop on Programming Abstractions and Interactive Notations, Tools, and Environments10.1145/3563836.3568727(48-56)Online publication date: 29-Nov-2022
  • (2011)ReferencesDesign for Embedded Image Processing on FPGAs10.1002/9780470828519.refs(441-473)Online publication date: 2-Jun-2011
  • (2010)Notations for Multiphase PipelinesProceedings of the 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications10.1109/DELTA.2010.29(212-216)Online publication date: 13-Jan-2010
  • (2009)User evaluation and overview of a visual language for real time image processing on FPGAsProceedings of the 10th International Conference NZ Chapter of the ACM's Special Interest Group on Human-Computer Interaction10.1145/1577782.1577798(85-92)Online publication date: 6-Jul-2009
  • (2008)A Visual Notation for Processor and Resource Scheduling4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)10.1109/DELTA.2008.76(296-301)Online publication date: Jan-2008

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