Article

Energy optimality and variability in subthreshold design

Authors:

Bo Zhai,

Xinlin WangAuthors Info & Claims

ISLPED '06: Proceedings of the 2006 international symposium on Low power electronics and design

Pages 363 - 365

https://doi.org/10.1145/1165573.1165660

Published: 04 October 2006 Publication History

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Abstract

Recent progress in the development of subthreshold circuit design techniques has created the opportunity for dramatic energy reductions in many applications. However, energy efficiency comes at the price of timing and energy variability due to process variations. We explore energy optimality in the subthreshold regime, discuss variability in this region, and highlight the energy and variability characteristics of a real subthreshold design.

References

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[2]

B. Zhai, et al., "A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency," VLSI Circuits Symposium, 2006.

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[3]

B. Calhoun, A. Wang, A. Chandrakasan, "Device sizing for minimum energy operation in subthreshold circuits," CICC, 2004, pp. 95--98.

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B. Zhai, S. Hanson, D. Blaauw, D. Sylvester, "Analysis and Mitigation of Variability in Subthreshold Design," ISLPED, 2005, pp. 20--25.

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W. Haensch, et al., " Silicon CMOS devices beyond scaling," IBM J. Res. & Dev. 50,No. 4, pp. 339--362.

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J. Kwong, A. Chandrakasan, "Variation-Driven Device Sizing for Minimum Energy Sub-threshold Circuits," ISLPED, 2006.

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Cited By

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Jain SLin LAlioto M(2020)Automated Design of Reconfigurable Microarchitectures for Accelerators Under Wide-Voltage ScalingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.295095928:3(777-790)Online publication date: Mar-2020
https://doi.org/10.1109/TVLSI.2019.2950959
Jain SLin LAlioto MJain SLin LAlioto M(2020)Automated Design Flows and Run-Time Optimization for Reconfigurable MicroarchitecuresAdaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling10.1007/978-3-030-38796-9_3(55-92)Online publication date: 28-Feb-2020
https://doi.org/10.1007/978-3-030-38796-9_3
Zadeh SYtterdal TAunet S(2019)Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI Technology2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)10.1109/NORCHIP.2019.8906939(1-6)Online publication date: Oct-2019
https://doi.org/10.1109/NORCHIP.2019.8906939
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Index Terms

Energy optimality and variability in subthreshold design
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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Information & Contributors

Information

Published In

ISLPED '06: Proceedings of the 2006 international symposium on Low power electronics and design

October 2006

446 pages

ISBN:1595934626

DOI:10.1145/1165573

General Chairs:
Wolfgang Nebel
University of Oldenburg and OFFIS
,
Mircea Stan
University of Virginia
,
Anand Raghunathan
NEC Laboratories America
,
Program Chairs:
Joerg Henkel
University of Karlsruhe
,
Diana Marculescu
Carnegie Mellon University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 04 October 2006

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ISLPED06

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ISLPED06: International Symposium on Low Power Electronics and Design

October 4 - 6, 2006

Bavaria, Tegernsee, Germany

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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Jain SLin LAlioto M(2020)Automated Design of Reconfigurable Microarchitectures for Accelerators Under Wide-Voltage ScalingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.295095928:3(777-790)Online publication date: Mar-2020
https://doi.org/10.1109/TVLSI.2019.2950959
Jain SLin LAlioto MJain SLin LAlioto M(2020)Automated Design Flows and Run-Time Optimization for Reconfigurable MicroarchitecuresAdaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling10.1007/978-3-030-38796-9_3(55-92)Online publication date: 28-Feb-2020
https://doi.org/10.1007/978-3-030-38796-9_3
Zadeh SYtterdal TAunet S(2019)Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI Technology2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)10.1109/NORCHIP.2019.8906939(1-6)Online publication date: Oct-2019
https://doi.org/10.1109/NORCHIP.2019.8906939
Zadeh SYtterdal TAunet S(2019)Ultra-Low Voltage Subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone Adder2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)10.1109/NORCHIP.2019.8906917(1-7)Online publication date: Oct-2019
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Jain SLin LAlioto M(2018)Dynamically Adaptable Pipeline for Energy-Efficient Microarchitectures Under Wide Voltage ScalingIEEE Journal of Solid-State Circuits10.1109/JSSC.2017.276840653:2(632-641)Online publication date: Feb-2018
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Wu TLi HHuang PRahimi ARabaey JWong HShulaker MMitra S(2018)Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study2018 IEEE International Solid - State Circuits Conference - (ISSCC)10.1109/ISSCC.2018.8310399(492-494)Online publication date: Feb-2018
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Rana MCanal RAmat ERubio A(2017)Statistical Analysis and Comparison of 2T and 3T1D e-DRAM Minimum Energy OperationIEEE Transactions on Device and Materials Reliability10.1109/TDMR.2017.266761917:1(42-51)Online publication date: Mar-2017
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Jain SLin LAlioto M(2017)Design-Oriented Energy Models for Wide Voltage Scaling Down to the Minimum Energy PointIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2017.273654064:12(3115-3125)Online publication date: Dec-2017
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Alioto M(2017)Near-Threshold Digital Circuits for Nearly-Minimum Energy ProcessingEnabling the Internet of Things10.1007/978-3-319-51482-6_4(95-148)Online publication date: 26-Jan-2017
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Han JZhang YHuang SChen MZeng X(2016)An Area-Efficient Error-Resilient Ultralow-Power Subthreshold ECG ProcessorIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2016.253815863:10(984-988)Online publication date: Oct-2016
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Utilizing reverse short channel effect for optimal subthreshold circuit design

Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic---Mitigation at Technology and Circuit Levels

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