Article

Hybrid transactional memory

Authors:

Alexandra Fedorova,

Victor Luchangco,

Daniel NussbaumAuthors Info & Claims

ASPLOS XII: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems

Pages 336 - 346

https://doi.org/10.1145/1168857.1168900

Published: 20 October 2006 Publication History

Abstract

Transactional memory (TM) promises to substantially reduce the difficulty of writing correct, efficient, and scalable concurrent programs. But "bounded" and "best-effort" hardware TM proposals impose unreasonable constraints on programmers, while more flexible software TM implementations are considered too slow. Proposals for supporting "unbounded" transactions in hardware entail significantly higher complexity and risk than best-effort designs.We introduce Hybrid Transactional Memory (HyTM), an approach to implementing TMin software so that it can use best effort hardware TM (HTM) to boost performance but does not depend on HTM. Thus programmers can develop and test transactional programs in existing systems today, and can enjoy the performance benefits of HTM support when it becomes available.We describe our prototype HyTM system, comprising a compiler and a library. The compiler allows a transaction to be attempted using best-effort HTM, and retried using the software library if it fails. We have used our prototype to "transactify" part of the Berkeley DB system, as well as several benchmarks. By disabling the optional use of HTM, we can run all of these tests on existing systems. Furthermore, by using a simulated multiprocessor with HTM support, we demonstrate the viability of the HyTM approach: it can provide performance and scalability approaching that of an unbounded HTM implementation, without the need to support all transactions with complicated HTM support.

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Hybrid transactional memory

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cover image ACM Conferences

ASPLOS XII: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems

October 2006

440 pages

ISBN:1595934510

DOI:10.1145/1168857

General Chair:
John Paul Shen
Intel Corp.
,
Program Chair:
Margaret R. Martonosi
Princeton University

ACM SIGARCH Computer Architecture News Volume 34, Issue 5
Proceedings of the 2006 ASPLOS Conference
December 2006
425 pages
ISSN:0163-5964
DOI:10.1145/1168919
Issue’s Table of Contents
ACM SIGOPS Operating Systems Review Volume 40, Issue 5
Proceedings of the 2006 ASPLOS Conference
December 2006
425 pages
ISSN:0163-5980
DOI:10.1145/1168917
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ACM SIGPLAN Notices Volume 41, Issue 11
Proceedings of the 2006 ASPLOS Conference
November 2006
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ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/1168918
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Copyright © 2006 ACM.

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Published: 20 October 2006

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transactional memory

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Overall Acceptance Rate 535 of 2,713 submissions, 20%

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https://doi.org/10.1016/j.jpdc.2023.104779
Jain AKadiyala DDaglis A(2023)Safety Hints for HTM Capacity Abort Mitigation2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071113(206-219)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10071113
Srivastava ABrown TLee JAgrawal KSpear M(2022)Elimination (a,b)-trees with fast, durable updatesProceedings of the 27th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/3503221.3508441(416-430)Online publication date: 2-Apr-2022
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Cai ZBlackburn SBond MWang ZWrigstad T(2021)Understanding and utilizing hardware transactional memory capacityProceedings of the 2021 ACM SIGPLAN International Symposium on Memory Management10.1145/3459898.3463901(1-14)Online publication date: 22-Jun-2021
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Lepers BBalmau OGupta KZwaenepoel WLu SHowell J(2020)KVell+Proceedings of the 14th USENIX Conference on Operating Systems Design and Implementation10.5555/3488766.3488790(425-441)Online publication date: 4-Nov-2020
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Chen DGibbons PMowry T(2020)TardisTMProceedings of the Eleventh International Workshop on Programming Models and Applications for Multicores and Manycores10.1145/3380536.3380538(1-10)Online publication date: 22-Feb-2020
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Piatka CAmslinger RHaas FWeis SAltmeyer SUngerer T(2020)Investigating Transactional Memory for High Performance Embedded SystemsArchitecture of Computing Systems – ARCS 202010.1007/978-3-030-52794-5_8(97-108)Online publication date: 9-Jul-2020
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