Article

Adapting compilation techniques to enhance the packing of instructions into registers

Authors:

Gary TysonAuthors Info & Claims

CASES '06: Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems

Pages 43 - 53

https://doi.org/10.1145/1176760.1176768

Published: 22 October 2006 Publication History

Abstract

The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Traditional compiler optimizations are often tuned for improving general architectural constraints, yet these heuristics may not be as beneficial to less conventional designs. Instruction packing is a recently developed compiler/architectural approach for reducing energy consumption, code size, and execution time by placing the frequently occurring instructions into an Instruction Register File (IRF). Multiple IRF instructions are made accessible via special packed instruction formats. This paper presents the design and analysis of a compilation framework and its associated optimizations for improving the efficiency of instruction packing. We show that several new heuristics can be developed for IRF promotion, instruction selection, register re-assignment and instruction scheduling, leading to significant reductions in energy consumption, code size, and/or execution time when compared to results using a standard optimizing compiler targeting the IRF.

References

[1]

T. Austin, E. Larson, and D. Ernst. SimpleScalar: An infrastructure for computer system modeling. IEEE Computer, 35:59--67, February 2002.

Digital Library

[2]

M. E. Benitez and J. W. Davidson. A portable global optimizer and linker. In Proceedings of the SIGPLAN'88 conference on Programming Language Design and Implementation, pages 329--338. ACM Press, 1988.

Digital Library

[3]

D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proceedings of the 27th annual International Symposium on Computer Architecture, pages 83--94, New York, NY, USA, 2000. ACM Press.

Digital Library

[4]

K. Cooper and N. McIntosh. Enhanced code compression for embedded risc processors. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, pages 139--149, May 1999.

Digital Library

[5]

M. L. Corliss, E. C. Lewis, and A. Roth. A DISE implementation of dynamic code decompression. In Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems, pages 232--243, June 2003.

Digital Library

[6]

S. K. Debray, W. Evans, R. Muth, and B. DeSutter. Compiler techniques for code compaction. ACM Transactions on Programming Languages and Systems, 22(2):378--415, March 2000.

Digital Library

[7]

C. W. Fraser, E. W. Myers, and A. L. Wendt. Analyzing and compressing assembly code. In Proceedings of the SIGPLAN'84 Symposium on Compiler Construction, pages 117--121, June 1984.

Digital Library

[8]

A. Gordon-Ross, S. Cotterell, and F. Vahid. Tiny instruction caches for low power embedded systems. Trans. on Embedded Computing Sys., 2(4):449--481, 2003.

Digital Library

[9]

M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. MiBench: A free, commercially representative embedded benchmark suite. IEEE 4th Annual Workshop on Workload Characterization, December 2001.

Digital Library

[10]

S. Hines, J. Green, G. Tyson, and D. Whalley. Improving program efficiency by packing instructions into registers. In Proceedings of the 2005 ACM/IEEE International Symposium on Computer Architecture, pages 260--271. IEEE Computer Society, 2005.

Digital Library

[11]

S. Hines, G. Tyson, and D. Whalley. Improving the energy and execution efficiency of a small instruction cache by using an instruction register file. In Proceedings of the 2nd Watson Conference on Interaction between Architecture, Circuits, and Compilers, pages 160--169, September 2005.

[12]

S. Hines, G. Tyson, and D. Whalley. Reducing instruction fetch cost by packing instructions into register windows. In Proceedings of the 38th annual ACM/IEEE International Symposium on Microarchitecture, pages 19--29. IEEE Computer Society, November 2005.

Digital Library

[13]

J. Kin, M. Gupta, and W. H. Mangione-Smith. The filter cache: An energy efficient memory structure. In Proceedings of the 1997 International Symposium on Microarchitecture, pages 184--193, 1997.

Digital Library

[14]

L. Lee, B. Moyer, and J. Arends. Instruction fetch energy reduction using loop caches for embedded applications with small tight loops. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 267--269, 1999.

Digital Library

[15]

C. Lefurgy, P. Bird, I. -C. Chen, and T. Mudge. Improving code density using compression techniques. In Proceedings of the 1997 International Symposium on Microarchitecture, pages 194--203, December 1997.

Digital Library

[16]

Montanaro J., et al. A 160-mhz, 32-b, 0. 5-W CMOS RISC microprocessor. Digital Tech. J., 9(1):49--62, 1997.

Digital Library

[17]

D. A. Padua and M. J. Wolfe. Advanced compiler optimizations for supercomputers. Commun. ACM, 29(12):1184--1201, 1986.

Digital Library

[18]

H. Pan and K. Asanović. Heads and Tails: A variable-length instruction format supporting parallel fetch and decode. In Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pages 168--175. ACM Press, 2001.

Digital Library

[19]

K. Pettis and R. C. Hansen. Profile guided code positioning. In Proceedings of the ACM SIGPLAN 1990 conference on Programming Language Design and Implementation, pages 16--27, New York, NY, USA, 1990. ACM Press.

Digital Library

[20]

S. Segars, K. Clarke, and L. Goudge. Embedded control problems, Thumb, and the ARM7TDMI. IEEE Micro, 15(5):22--30, October 1995.

Digital Library

[21]

N. J. Warter, G. E. Haab, K. Subramanian, and J. W. Bockhaus. Enhanced modulo scheduling for loops with conditional branches. In Proceedings of the 25th annual international symposium on Microarchitecture, pages 170--179, Los Alamitos, CA, USA, 1992. IEEE Computer Society Press.

Digital Library

[22]

D. Weaver and T. Germond. The SPARC Architecture Manual, 1994.

[23]

S. J. Wilton and N. P. Jouppi. CACTI: An enhanced cache access and cycle time model. IEEE Journal of Solid State Circuits, 31(5):677--688, May 1996.

Cited By

Collin MBrorsson MOberg J(2011)A performance and energy exploration of dictionary code compression architecturesProceedings of the 2011 International Green Computing Conference and Workshops10.1109/IGCC.2011.6008584(1-8)Online publication date: 25-Jul-2011
https://dl.acm.org/doi/10.1109/IGCC.2011.6008584
Jung Y(2011)A post-manufacturing language-adaptive embedded processor system2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)10.1109/AHS.2011.5963931(161-168)Online publication date: Jun-2011
https://doi.org/10.1109/AHS.2011.5963931
Collin MBrorsson M(2009)Two-Level Dictionary Code CompressionProceedings of the 7th annual IEEE/ACM International Symposium on Code Generation and Optimization10.1109/CGO.2009.16(231-242)Online publication date: 22-Mar-2009
https://dl.acm.org/doi/10.1109/CGO.2009.16
Show More Cited By

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Adapting compilation techniques to enhance the packing of instructions into registers

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Published In

cover image ACM Conferences

CASES '06: Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems

October 2006

448 pages

ISBN:1595935436

DOI:10.1145/1176760

General Chairs:
Seongsoo Hong
Seoul National University
,
Wayne Wolf
Princeton University
,
Program Chairs:
Krisztian Flautner
ARM Ltd.
,
Taewhan Kim
Seoul National University

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 22 October 2006

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ESWEEK06

Sponsor:

ESWEEK06: Second Embedded Systems Week 2006

October 22 - 25, 2006

Seoul, Korea

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Overall Acceptance Rate 52 of 230 submissions, 23%

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Cited By

Collin MBrorsson MOberg J(2011)A performance and energy exploration of dictionary code compression architecturesProceedings of the 2011 International Green Computing Conference and Workshops10.1109/IGCC.2011.6008584(1-8)Online publication date: 25-Jul-2011
https://dl.acm.org/doi/10.1109/IGCC.2011.6008584
Jung Y(2011)A post-manufacturing language-adaptive embedded processor system2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)10.1109/AHS.2011.5963931(161-168)Online publication date: Jun-2011
https://doi.org/10.1109/AHS.2011.5963931
Collin MBrorsson M(2009)Two-Level Dictionary Code CompressionProceedings of the 7th annual IEEE/ACM International Symposium on Code Generation and Optimization10.1109/CGO.2009.16(231-242)Online publication date: 22-Mar-2009
https://dl.acm.org/doi/10.1109/CGO.2009.16
Whalley DTyson G(2008)Enhancing the effectiveness of utilizing an instruction register file2008 IEEE International Symposium on Parallel and Distributed Processing10.1109/IPDPS.2008.4536413(1-5)Online publication date: Apr-2008
https://doi.org/10.1109/IPDPS.2008.4536413
Collin MBrorsson M(2008)Improving code density of embedded software using a 2-level dictionary code compression architecture2008 13th Asia-Pacific Computer Systems Architecture Conference10.1109/APCSAC.2008.4625452(1-8)Online publication date: Aug-2008
https://doi.org/10.1109/APCSAC.2008.4625452
Hines STyson GWhalley D(2007)Addressing instruction fetch bottlenecks by using an instruction register fileACM SIGPLAN Notices10.1145/1273444.125480042:7(165-174)Online publication date: 13-Jun-2007
https://dl.acm.org/doi/10.1145/1273444.1254800
Hines STyson GWhalley DPande SLi Z(2007)Addressing instruction fetch bottlenecks by using an instruction register fileProceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems10.1145/1254766.1254800(165-174)Online publication date: 13-Jun-2007
https://dl.acm.org/doi/10.1145/1254766.1254800

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