Article

Design of mixed gates for leakage reduction

Authors:

Dirk TimmermannAuthors Info & Claims

GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI

Pages 263 - 268

https://doi.org/10.1145/1228784.1228851

Published: 11 March 2007 Publication History

Abstract

Leakage power dissipation is one of the most critical factors for the overall current dissipation and future designs. However, design techniques for the reduction of leakage power should not decrease design performance. Therefore, an enhanced Dual Vth/Dual Tox CMOS ap-proach is presented which applies mixed gates consisting of different transistor types. The paper introduces the new and fundamental idea of different gate types before the various possible configurations are analyzed. This is followed by extraction and exploration of design rules and recommendations. Simulations of modified ISCAS'85 designs show an average leakage reduction of 60% at constant performance compared to raw designs. This corresponds to an additional reduction of 20% compared to previous Dual Vth/Dual Tox CMOS approaches.

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Cited By

Bastos RTorres FBastos RTorres F(2019)Enhancing the Design of Body Built-In Sensor ArchitecturesOn-Chip Current Sensors for Reliable, Secure, and Low-Power Integrated Circuits10.1007/978-3-030-29353-6_4(55-77)Online publication date: 1-Oct-2019
https://doi.org/10.1007/978-3-030-29353-6_4
Shauly E(2012)CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout ConsiderationsJournal of Low Power Electronics and Applications10.3390/jlpea20100012:1(1-29)Online publication date: 27-Jan-2012
https://doi.org/10.3390/jlpea2010001
Torres FBastos R(2012)Robust modular Bulk Built-in Current Sensors for detection of transient faults2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)10.1109/SBCCI.2012.6344422(1-6)Online publication date: Aug-2012
https://doi.org/10.1109/SBCCI.2012.6344422
Show More Cited By

Index Terms

Design of mixed gates for leakage reduction
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

cover image ACM Conferences

GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI

March 2007

626 pages

ISBN:9781595936059

DOI:10.1145/1228784

General Chairs:
Hai Zhou
Northwestern University
,
Enrico Macii
Politecnico di Torino
,
Program Chairs:
Zhiyuan Yan
Lehigh University
,
Yehia Massoud
Rice University

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 11 March 2007

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GLSVLSI07

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GLSVLSI07: Great Lakes Symposium on VLSI 2007

March 11 - 13, 2007

Stresa-Lago Maggiore, Italy

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Citations

Cited By

Bastos RTorres FBastos RTorres F(2019)Enhancing the Design of Body Built-In Sensor ArchitecturesOn-Chip Current Sensors for Reliable, Secure, and Low-Power Integrated Circuits10.1007/978-3-030-29353-6_4(55-77)Online publication date: 1-Oct-2019
https://doi.org/10.1007/978-3-030-29353-6_4
Shauly E(2012)CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout ConsiderationsJournal of Low Power Electronics and Applications10.3390/jlpea20100012:1(1-29)Online publication date: 27-Jan-2012
https://doi.org/10.3390/jlpea2010001
Torres FBastos R(2012)Robust modular Bulk Built-in Current Sensors for detection of transient faults2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)10.1109/SBCCI.2012.6344422(1-6)Online publication date: Aug-2012
https://doi.org/10.1109/SBCCI.2012.6344422
Mohanty SKougianos EOkobiah O(2012)Optimal design of a dual-oxide nano-CMOS universal level converter for multi-Vdd SoCsAnalog Integrated Circuits and Signal Processing10.1007/s10470-012-9887-772:2(451-467)Online publication date: 1-Aug-2012
https://dl.acm.org/doi/10.1007/s10470-012-9887-7
Mohanty SPanigrahi B(2009)ILP based leakage optimization during nano-CMOS RTL synthesis: A DOXCMOS Versus DTCMOS perspective2009 World Congress on Nature & Biologically Inspired Computing (NaBIC)10.1109/NABIC.2009.5393744(1367-1372)Online publication date: Dec-2009
https://doi.org/10.1109/NABIC.2009.5393744
Mohanty SPradhan D(2008)ULSACM Journal on Emerging Technologies in Computing Systems10.1145/1773814.17738196:2(1-26)Online publication date: 18-Jun-2008
https://dl.acm.org/doi/10.1145/1773814.1773819
Cornelius CSill FSämrow HSalzmann JTimmermann Dda Silva DLubaszewski MRenovell MGupta R(2008)Encountering gate oxide breakdown with shadow transistors to increase reliabilityProceedings of the 21st annual symposium on Integrated circuits and system design10.1145/1404371.1404407(111-116)Online publication date: 1-Sep-2008
https://dl.acm.org/doi/10.1145/1404371.1404407
Ghai DMohanty SKougianos E(2008)A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCs9th International Symposium on Quality Electronic Design (isqed 2008)10.1109/ISQED.2008.4479735(257-260)Online publication date: Mar-2008
https://doi.org/10.1109/ISQED.2008.4479735

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