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Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology

Published: 11 March 2007 Publication History

Abstract

In this paper, we present a JPEG decoder implemented in our ODYSSEY design methodology. We start with an object-oriented JPEG decoder model. The total operation from modeling to implementation is done automatically by our EDA tool-set in about 10 hours. The resultant system is a JPEG decoder ASIP whose hardware part is implemented on FPGA logic blocks and software part runs on a MicroBlaze processor. This ASIP can be extended by software routines to implement the motion JPEG or MPEG2 decoding algorithms. We implemented our system on ML402 FPGA-based prototype board. Experimental results show that our ASIP implementation is comparable to other approaches while our approach enables quick and easy development of an ASIP using our EDA tool-set and effectively reduces time-to-market.

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M. Goudarzi, S. Hessabi, A. Mycroft, "Object-Oriented Embedded System Development Based on Synthesis and Reuse of OO-ASIPs", Journal of Universal Computer Science, Vol. 10, No. 9, PP. 123--135.
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  • (2008)The ODYSSEY approach to early simulation-based equivalence checking at ESL level using automatically generated executable transaction-level modelMicroprocessors & Microsystems10.1016/j.micpro.2008.04.00132:7(364-374)Online publication date: 1-Oct-2008

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  1. Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology

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      cover image ACM Conferences
      GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSI
      March 2007
      626 pages
      ISBN:9781595936059
      DOI:10.1145/1228784
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 11 March 2007

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      Author Tags

      1. ASIP
      2. JPEG
      3. ODYSSEY
      4. embedded systems

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      GLSVLSI07: Great Lakes Symposium on VLSI 2007
      March 11 - 13, 2007
      Stresa-Lago Maggiore, Italy

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      • (2008)The ODYSSEY approach to early simulation-based equivalence checking at ESL level using automatically generated executable transaction-level modelMicroprocessors & Microsystems10.1016/j.micpro.2008.04.00132:7(364-374)Online publication date: 1-Oct-2008

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