Article

Stochastic interconnect layout sensitivity model

Authors:

Payman Zarkesh-Ha,

Ken DonigerAuthors Info & Claims

SLIP '07: Proceedings of the 2007 international workshop on System level interconnect prediction

Pages 9 - 14

https://doi.org/10.1145/1231956.1231959

Published: 17 March 2007 Publication History

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Abstract

Semiconductor manufacturing yield is determined by the defect density and critical area i.e. that portion of the layout in which the occurrence of a defect results in yield loss. In this paper, we define layout sensitivity as the ratio of critical area to the layout area. Utilizing the basic probability theory, a rigorous derivation of layout sensitivity for random logic network is performed. This model is compared to actual critical area distributions for a modern microprocessor design. A methodology to calculate the layout sensitivity pattern for a complex layout is proposed.

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Zarkesh-Ha PShahi A(2010)Logic Gate Failure Characterization for Nanoelectronic EDA ToolsProceedings of the 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems10.1109/DFT.2010.9(16-23)Online publication date: 6-Oct-2010
https://dl.acm.org/doi/10.1109/DFT.2010.9
Chen BChen HHuang LPan PLombardi FBhanja SMassoud YBahar R(2009)A stochastic-based efficient critical area extractor on OpenAccess platformProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531592(197-202)Online publication date: 10-May-2009
https://dl.acm.org/doi/10.1145/1531542.1531592
Ghaida RDoniger KZarkesh-Ha P(2009)Random Yield Prediction Based on a Stochastic Layout Sensitivity ModelIEEE Transactions on Semiconductor Manufacturing10.1109/TSM.2009.202482122:3(329-337)Online publication date: Aug-2009
https://doi.org/10.1109/TSM.2009.2024821
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Index Terms

Stochastic interconnect layout sensitivity model
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Modeling methodologies
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Partitioning and floorplanning
  2. Hardware validation
    1. Functional verification
      1. Simulation and emulation

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Published In

SLIP '07: Proceedings of the 2007 international workshop on System level interconnect prediction

March 2007

120 pages

ISBN:9781595936226

DOI:10.1145/1231956

General Chair:
Andrew Kennings
University of Waterloo, Canada
,
Program Chair:
Ion Mandoiu
University of Connecticut, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 17 March 2007

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SLIP07: International Workshop on System Level Interconnect Prediction

March 17 - 18, 2007

Texas, Austin, USA

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Overall Acceptance Rate 6 of 8 submissions, 75%

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Zarkesh-Ha PShahi A(2010)Logic Gate Failure Characterization for Nanoelectronic EDA ToolsProceedings of the 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems10.1109/DFT.2010.9(16-23)Online publication date: 6-Oct-2010
https://dl.acm.org/doi/10.1109/DFT.2010.9
Chen BChen HHuang LPan PLombardi FBhanja SMassoud YBahar R(2009)A stochastic-based efficient critical area extractor on OpenAccess platformProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531592(197-202)Online publication date: 10-May-2009
https://dl.acm.org/doi/10.1145/1531542.1531592
Ghaida RDoniger KZarkesh-Ha P(2009)Random Yield Prediction Based on a Stochastic Layout Sensitivity ModelIEEE Transactions on Semiconductor Manufacturing10.1109/TSM.2009.202482122:3(329-337)Online publication date: Aug-2009
https://doi.org/10.1109/TSM.2009.2024821
Ghaida RZarkesh-Ha P(2009)A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow InterconnectsJournal of Electronic Testing: Theory and Applications10.1007/s10836-008-5079-x25:1(67-77)Online publication date: 1-Feb-2009
https://dl.acm.org/doi/10.1007/s10836-008-5079-x
Ghaida RZarkesh-Ha P(2007)Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)10.1109/DFT.2007.12(59-67)Online publication date: Sep-2007
https://doi.org/10.1109/DFT.2007.12

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A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects

Layout generator for transistor-level high-density regular circuits

A Reduction of Grid-Bag Layout to Auckland Layout

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