Article

Counterflow pipelining: architectural support for preemption in asynchronous systems using anti-tokens

Authors:

Manoj Ampalam,

Montek SinghAuthors Info & Claims

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Pages 611 - 618

https://doi.org/10.1145/1233501.1233627

Published: 05 November 2006 Publication History

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Abstract

This paper introduces a novel approach to efficiently implement several useful architectural features in asynchronous application-specific ICs (ASICs). These features include speculation, preemption, and eager evaluation, which have so far only been available on CPUs, and have not been adequately investigated for custom ASICs.

For the efficient implementation of the new architectural features, a radically new approach inspired by Sproull's counterflow pipelines [7] is proposed. The key idea is to allow special commands, called anti-tokens, to be propagated in a direction opposite to that of data, allowing certain computations to be killed before they are completed, if their results are no longer required.

The net impact is a significant improvement in the throughput of a certain class of systems---e.g., those involving conditional computation---where a bottleneck pipeline stage can often be preempted if its result is determined to be no longer needed. Experimental results indicate that our approach can improve the system throughput by a factor of up to 2.2x, along with an energy savings of up to 27%.

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J. Hensley, A. Lastra, and M. Singh. A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier. In Proc. Int. Symposium on Advanced Research in Asynchronous Circuits and Systems, Mar. 2005.

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M. Singh and S. M. Nowick. MOUSETRAP: Ultra-high-speed transition-signaling asynchronous pipelines. In Proc. Int. Conf. Computer Design (ICCD), pages 9--17, 2001.

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R. F. Sproull, I. E. Sutherland, and C. E. Molnar. The counterflow pipeline processor architecture. IEEE Design & Test of Computers, 11(3):48--59, Fall 1994.

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Cortadella JGalceran-Oms MKishinevsky MSapatnekar S(2015)RTL Synthesis: From Logic Synthesis to Automatic PipeliningProceedings of the IEEE10.1109/JPROC.2015.2456189103:11(2061-2075)Online publication date: Nov-2015
https://doi.org/10.1109/JPROC.2015.2456189
Casu M(2011)Half-buffer retiming and token cages for synchronous elastic circuitsIET Computers & Digital Techniques10.1049/iet-cdt.2010.01165:4(318)Online publication date: 2011
https://doi.org/10.1049/iet-cdt.2010.0116
(2010)Elastic systemsProceedings of the Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign10.1109/MEMCOD.2010.5558639(149-158)Online publication date: 1-Jul-2010
https://dl.acm.org/doi/10.1109/MEMCOD.2010.5558639
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Counterflow pipelining: architectural support for preemption in asynchronous systems using anti-tokens
1. Hardware

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Published In

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

November 2006

147 pages

ISBN:1595933891

DOI:10.1145/1233501

General Chair:
Soha Hassoun
Tufts Univ., Medford, MA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 05 November 2006

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ICCAD06: The International Conference on Computer-Aided Design 2006

November 5 - 9, 2006

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cortadella JGalceran-Oms MKishinevsky MSapatnekar S(2015)RTL Synthesis: From Logic Synthesis to Automatic PipeliningProceedings of the IEEE10.1109/JPROC.2015.2456189103:11(2061-2075)Online publication date: Nov-2015
https://doi.org/10.1109/JPROC.2015.2456189
Casu M(2011)Half-buffer retiming and token cages for synchronous elastic circuitsIET Computers & Digital Techniques10.1049/iet-cdt.2010.01165:4(318)Online publication date: 2011
https://doi.org/10.1049/iet-cdt.2010.0116
(2010)Elastic systemsProceedings of the Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign10.1109/MEMCOD.2010.5558639(149-158)Online publication date: 1-Jul-2010
https://dl.acm.org/doi/10.1109/MEMCOD.2010.5558639
Galceran-Oms MCortadella JKishinevsky M(2009)Speculation in elastic systemsProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1629989(292-295)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1629989
Bufistov DCortadella JGalceran-Oms MJúlvez JKishinevsky M(2009)Retiming and recycling for elastic systems with early evaluationProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1629988(288-291)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1629988
Carmona JCortadella JKishinevsky MTaubin A(2009)Elastic circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.203043628:10(1437-1455)Online publication date: 1-Oct-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2030436
Li CCarloni L(2009)Leveraging local intracore information to increase global performance in block-based design of systems-on-chipIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.200915728:2(165-178)Online publication date: 1-Feb-2009
https://dl.acm.org/doi/10.1109/TCAD.2008.2009157
Poliakov IKhomenko VYakovlev A(2009)Workcraft --- A Framework for Interpreted Graph ModelsProceedings of the 30th International Conference on Applications and Theory of Petri Nets10.1007/978-3-642-02424-5_21(333-342)Online publication date: 18-Jun-2009
https://dl.acm.org/doi/10.1007/978-3-642-02424-5_21
Sokolov DPoliakov IYakovlev A(2008)Analysis of Static Data Flow StructuresFundamenta Informaticae10.5555/2366276.236628388:4(581-610)Online publication date: 1-Dec-2008
https://dl.acm.org/doi/10.5555/2366276.2366283
Kam TKishinevsky MCortadella JGalceran-Oms MNassif SRoychowdhury J(2008)Correct-by-construction microarchitectural pipeliningProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509558(434-441)Online publication date: 10-Nov-2008
https://dl.acm.org/doi/10.5555/1509456.1509558
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Software pipelining: an effective scheduling technique for VLIW machines

Custom embedded counterflow pipelines

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Software pipelining: an effective scheduling technique for VLIW machines

Custom embedded counterflow pipelines

Multiple-pass pipelining: enhancing in-order microarchitectures to out-of-order performance

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