Article

Examining ACE analysis reliability estimates using fault-injection

Authors:

Nicholas J. Wang,

Sanjay J. PatelAuthors Info & Claims

ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture

Pages 460 - 469

https://doi.org/10.1145/1250662.1250719

Published: 09 June 2007 Publication History

Abstract

ACE analysis is a technique to provide an early reliability estimate for microprocessors. ACE analysis couples data from abstract performance models with low level design details to identify and rule out transient faults that will not cause incorrect execution. While many transient faults are analyzable in ACE analysis frameworks, some are not. As a result, ACE analysis is conservative and provides a lower bound for the reliability of a processor design. Bounding the reliability of a design is useful since it can guarantee that the given design will meet reliability goals.

In this work, we quantify and identify the sources of ACE analysis conservatism by comparing an ACE analysis methodology against a rigorous fault-injection study. We evaluate two flavors of ACE analysis: a "simple" analysis and a refined analysis, finding that even the refined analysis overestimates the soft error vulnerability of an instruction scheduler by 2-3x. The conservatism stems from two key sources: from lack of detail in abstract performance models and from what we term Y-Bits, a result of the single-pass simulation methodology that is typical of ACE analysis. We also examine the efficacy of applying ACE analysis to a class of "partial coverage" error mitigation techniques. In particular, we perform a case study on one such technique and extrapolate our findings to others.

References

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Cited By

Nouri ENosrati NAsl HManavand MNavabi Z(2023)Multi-Level Fault Injection Methodology Using UVM-SystemC2023 IEEE East-West Design & Test Symposium (EWDTS)10.1109/EWDTS59469.2023.10297034(1-6)Online publication date: 22-Sep-2023
https://doi.org/10.1109/EWDTS59469.2023.10297034
Kritikakou ASentieys OHubert GHelen YCoulon JDeroux-Dauphin P(2022)Flodam: Cross-Layer Reliability Analysis Flow for Complex Hardware Designs2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774541(819-824)Online publication date: 14-Mar-2022
https://doi.org/10.23919/DATE54114.2022.9774541
Bosio ARebaudengo MSavino A(2022)Reliability assessment of FreeRTOS in Embedded Systems2022 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S)10.1109/DSN-S54099.2022.00019(28-30)Online publication date: Jun-2022
https://doi.org/10.1109/DSN-S54099.2022.00019
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Index Terms

Examining ACE analysis reliability estimates using fault-injection
1. Hardware
  1. Hardware test
  2. Robustness

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Published In

cover image ACM Conferences

ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture

June 2007

542 pages

ISBN:9781595937063

DOI:10.1145/1250662

General Chair:
Dean Tullsen
University of California, San Diego
,
Program Chair:
Brad Calder
Microsoft & University of California, San Diego

ACM SIGARCH Computer Architecture News Volume 35, Issue 2
May 2007
527 pages
ISSN:0163-5964
DOI:10.1145/1273440
Issue’s Table of Contents

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

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Published: 09 June 2007

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SPAA07: 19th ACM Symposium on Parallelism in Algorithms and Architectures

June 9 - 13, 2007

California, San Diego, USA

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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Cited By

Nouri ENosrati NAsl HManavand MNavabi Z(2023)Multi-Level Fault Injection Methodology Using UVM-SystemC2023 IEEE East-West Design & Test Symposium (EWDTS)10.1109/EWDTS59469.2023.10297034(1-6)Online publication date: 22-Sep-2023
https://doi.org/10.1109/EWDTS59469.2023.10297034
Kritikakou ASentieys OHubert GHelen YCoulon JDeroux-Dauphin P(2022)Flodam: Cross-Layer Reliability Analysis Flow for Complex Hardware Designs2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774541(819-824)Online publication date: 14-Mar-2022
https://doi.org/10.23919/DATE54114.2022.9774541
Bosio ARebaudengo MSavino A(2022)Reliability assessment of FreeRTOS in Embedded Systems2022 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S)10.1109/DSN-S54099.2022.00019(28-30)Online publication date: Jun-2022
https://doi.org/10.1109/DSN-S54099.2022.00019
Sorin DSorin D(2022)IntroductionFault Tolerant Computer Architecture10.1007/978-3-031-01723-0_1(1-17)Online publication date: 5-Mar-2022
https://doi.org/10.1007/978-3-031-01723-0_1
So HDidehban MKo YJeyapaul RKim JKim YLee KShrivastava A(2021)Revisiting Symptom-Based Fault Tolerant Techniques against Soft ErrorsElectronics10.3390/electronics1023302810:23(3028)Online publication date: 4-Dec-2021
https://doi.org/10.3390/electronics10233028
Casseau EDobias PSinnen ORodrigues GKastensmidt FSavino ADi Carlo SRebaudengo MBosio A(2021)Special Session: Operating Systems under test: an overview of the significance of the operating system in the resiliency of the computing continuum2021 IEEE 39th VLSI Test Symposium (VTS)10.1109/VTS50974.2021.9441042(1-10)Online publication date: 25-Apr-2021
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Papadimitriou GGizopoulos D(2021)Demystifying the System Vulnerability Stack: Transient Fault Effects Across the Layers2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA52012.2021.00075(902-915)Online publication date: Jun-2021
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Tsiokanos IPapadimitriou GGizopoulos DKarakonstantis G(2021)Boosting Microprocessor Efficiency: Circuit- and Workload-Aware Assessment of Timing Errors2021 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC53511.2021.00022(125-137)Online publication date: Nov-2021
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Previlon FKalra Ctiwari dKaeli D(2020)Characterizing and Exploiting Soft Error Vulnerability Phase Behavior in GPU ApplicationsIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2020.2991136(1-1)Online publication date: 2020
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(2020)On the Analysis of Real-time Operating System Reliability in Embedded Systems2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT50435.2020.9250861(1-6)Online publication date: 2020
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