Article

Simulating improbable events

Authors:

Suwen Yang,

Mark R. GreenstreetAuthors Info & Claims

DAC '07: Proceedings of the 44th annual Design Automation Conference

Pages 154 - 157

https://doi.org/10.1145/1278480.1278518

Published: 04 June 2007 Publication History

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Abstract

Circuits such as flip-flops, sense amplifiers and synchronizers can exhibit metastability failures that are undetectable given the numerical accuracy limitations of simulators such as HSPICE. We present a novel simulation technique that allows us to generate accurate waveforms for the metastability failures and similar events. We apply our method to two latches and a self-resetting circuit for clock-phase generation.

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Cited By

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Polzer THuemer FSteininger A(2019)An Experimental Study of Metastability-Induced Glitching BehaviorJournal of Circuits, Systems and Computers10.1142/S021812661940006128:supp01(1940006)Online publication date: 12-Dec-2019
https://doi.org/10.1142/S0218126619400061
Yang SLiu FLee V(2016)Asynchronously Controlled Frequency Locked Loop2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)10.1109/ASYNC.2016.8(3-10)Online publication date: May-2016
https://doi.org/10.1109/ASYNC.2016.8
Mak T(2012)Truncation error analysis of MTBF computation for multi-latch synchronizersMicroelectronics Journal10.1016/j.mejo.2011.09.01143:2(160-163)Online publication date: Feb-2012
https://doi.org/10.1016/j.mejo.2011.09.011
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Index Terms

Simulating improbable events
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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A synchronizer timing model, called the jitter model, which has general application to metastable reliability analysis, is proposed and analyzed. The jitter model is applied to show that redundancy cannot improve the metastable reliability of ...

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Published In

DAC '07: Proceedings of the 44th annual Design Automation Conference

June 2007

1016 pages

ISBN:9781595936271

DOI:10.1145/1278480

General Chair:
Steven P. Levitan
Univ. of Pittsburgh, Pittsburgh, PA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 04 June 2007

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DAC07: The 44th Annual Design Automation Conference 2007

June 4 - 8, 2007

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DAC '07 Paper Acceptance Rate 152 of 659 submissions, 23%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Polzer THuemer FSteininger A(2019)An Experimental Study of Metastability-Induced Glitching BehaviorJournal of Circuits, Systems and Computers10.1142/S021812661940006128:supp01(1940006)Online publication date: 12-Dec-2019
https://doi.org/10.1142/S0218126619400061
Yang SLiu FLee V(2016)Asynchronously Controlled Frequency Locked Loop2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)10.1109/ASYNC.2016.8(3-10)Online publication date: May-2016
https://doi.org/10.1109/ASYNC.2016.8
Mak T(2012)Truncation error analysis of MTBF computation for multi-latch synchronizersMicroelectronics Journal10.1016/j.mejo.2011.09.01143:2(160-163)Online publication date: Feb-2012
https://doi.org/10.1016/j.mejo.2011.09.011
Jones IYang SGreenstreet M(2009)Synchronizer Behavior and AnalysisProceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)10.1109/ASYNC.2009.8(117-126)Online publication date: 17-May-2009
https://dl.acm.org/doi/10.1109/ASYNC.2009.8
Teehan PGreenstreet MLemieux G(2007)A Survey and Taxonomy of GALS Design StylesIEEE Design & Test10.1109/MDT.2007.15124:5(418-428)Online publication date: 1-Sep-2007
https://dl.acm.org/doi/10.1109/MDT.2007.151

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Eleven Ways to Boost Your Synchronizer

Voltage-Boosted Synchronizers

The Jitter Model for Metastability and its Application to Redundant Synchronizers

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Eleven Ways to Boost Your Synchronizer

Voltage-Boosted Synchronizers

The Jitter Model for Metastability and its Application to Redundant Synchronizers

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