Article

Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies

Authors:

Saibal Mukhopadhyay,

Keunwoo Kim,

Ching-Te ChuangAuthors Info & Claims

ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design

Pages 20 - 25

https://doi.org/10.1145/1283780.1283786

Published: 27 August 2007 Publication History

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Abstract

This paper demonstrates viable device design options for low-leakage and robust SRAM in sub-50nm FD/SOI technology. We explore the possibilities of reducing the body-doping of FD/SOI devices with proper tuning of back-gate bias or gate workfunction to achieve a given leakage target. The reduction of body-doping density helps reduce the effect of the random dopant fluctuation (RDF), while the Vt and leakage are controlled using the back-gate bias. Our analysis show that, body-doping reduction combined with back-gate biasing is the most efficient FD/SOI device design for low-leakage and robust SRAM.

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Cited By

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Burignat SFlandre DMd Arshad MKilchytska VAndrieu FFaynot ORaskin J(2010)Substrate impact on threshold voltage and subthreshold slope of sub-32nm ultra thin SOI MOSFETs with thin buried oxide and undoped channelSolid-State Electronics10.1016/j.sse.2009.12.02154:2(213-219)Online publication date: Feb-2010
https://doi.org/10.1016/j.sse.2009.12.021
Kranti ABurignat SRaskin JArmstrong G(2009)Underlap channel UTBB MOSFETs for low—power analog/RF applications2009 10th International Conference on Ultimate Integration of Silicon10.1109/ULIS.2009.4897564(173-176)Online publication date: Mar-2009
https://doi.org/10.1109/ULIS.2009.4897564
Mukhopadhyay SKim KChuang C(2008)Device Design and Optimization Methodology for Leakage and Variability Reduction in Sub-45-nm FD/SOI SRAMIEEE Transactions on Electron Devices10.1109/TED.2007.91107355:1(152-162)Online publication date: Jan-2008
https://doi.org/10.1109/TED.2007.911073
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Index Terms

Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Static memory

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Published In

ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design

August 2007

432 pages

ISBN:9781595937094

DOI:10.1145/1283780

General Chairs:
Diana Marculescu
Carnegie Mellon University
,
Anand Raghunathan
NEC Laboratories America
,
Program Chairs:
Ali Keshavarzi
Intel Corporation
,
Vijaykrishnan Narayanan
Penn State University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 27 August 2007

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ISLPED07: International Symposium on Low Power Electronics and Design

August 27 - 29, 2007

OR, Portland, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Burignat SFlandre DMd Arshad MKilchytska VAndrieu FFaynot ORaskin J(2010)Substrate impact on threshold voltage and subthreshold slope of sub-32nm ultra thin SOI MOSFETs with thin buried oxide and undoped channelSolid-State Electronics10.1016/j.sse.2009.12.02154:2(213-219)Online publication date: Feb-2010
https://doi.org/10.1016/j.sse.2009.12.021
Kranti ABurignat SRaskin JArmstrong G(2009)Underlap channel UTBB MOSFETs for low—power analog/RF applications2009 10th International Conference on Ultimate Integration of Silicon10.1109/ULIS.2009.4897564(173-176)Online publication date: Mar-2009
https://doi.org/10.1109/ULIS.2009.4897564
Mukhopadhyay SKim KChuang C(2008)Device Design and Optimization Methodology for Leakage and Variability Reduction in Sub-45-nm FD/SOI SRAMIEEE Transactions on Electron Devices10.1109/TED.2007.91107355:1(152-162)Online publication date: Jan-2008
https://doi.org/10.1109/TED.2007.911073
Ching-Te Chuang Mukhopadhyay SJae-Joon Kim Keunwoo Kim Rao R(2007)High-performance SRAM in nanoscale CMOSProceedings of the 2007 IEEE International Workshop on Memory Technology, Design and Testing10.1109/MTDT.2007.4547603(4-12)Online publication date: 3-Dec-2007
https://dl.acm.org/doi/10.1109/MTDT.2007.4547603

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Design of a Highly Stable and Robust 10T SRAM Cell for Low-Power Portable Applications

Low-leakage robust SRAM cell design for sub-100nm technologies

Design and analysis of two low-power SRAM cell structures

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