Article

Compile-time decided instruction cache locking using worst-case execution paths

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CODES+ISSS '07: Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis

Pages 143 - 148

https://doi.org/10.1145/1289816.1289853

Published: 30 September 2007 Publication History

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Abstract

Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability is highly undesired for real-time systems. The Worst-Case Execution Time (WCET) of a software running on an embedded processor is one of the most important metrics during real-time system design. The WCET depends to a large extent on the total amount of time spent for memory accesses. In the presence of caches, WCET analysis must always assume a memory access to be a cache miss if it can not be guaranteed that it is a hit. Hence, WCETs for cached systems are imprecise due to the overestimation caused by the caches.

Modern caches can be controlled by software. The software can load parts of its code or of its data into the cache and lock the cache afterwards. Cache locking prevents the cache's contents from being flushed by deactivating the replacement. A locked cache is highly predictable and leads to very precise WCET estimates, because the uncertainty caused by the replacement strategy is eliminated completely.

This paper presents techniques exploring the lockdown of instruction caches at compile-time to minimize WCETs. In contrast to the current state of the art in the area of cache locking, our techniques explicitly take the worst-case execution path into account during each step of the optimization procedure. This way, we can make sure that always those parts of the code are locked in the I-cache that lead to the highest WCET reduction. The results demonstrate that WCET reductions from 54% up to 73% can be achieved with an acceptable amount of CPU seconds required for the optimization and WCET analyses themselves.

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Pandith O(2024)SGXFault: An Efficient Page Fault Handling Mechanism for SGX EnclavesIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2023.326816921:3(1173-1178)Online publication date: May-2024
https://doi.org/10.1109/TDSC.2023.3268169
Khayatian MMehrabian MAndert EGrimsley RLiang KHu YMcCormack IJoe-Wong CAldrich JIannucci BShrivastava A(2022)Plan B: Design Methodology for Cyber-Physical Systems Robust to Timing FailuresACM Transactions on Cyber-Physical Systems10.1145/35164496:3(1-39)Online publication date: 7-Sep-2022
https://dl.acm.org/doi/10.1145/3516449
Roozkhosh SMancuso R(2020)The Potential of Programmable Logic in the Middle: Cache Bleaching2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS48715.2020.00006(296-309)Online publication date: Apr-2020
https://doi.org/10.1109/RTAS48715.2020.00006
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Index Terms

Compile-time decided instruction cache locking using worst-case execution paths
1. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory
2. Software and its engineering
  1. Software notations and tools
    1. Compilers

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Published In

CODES+ISSS '07: Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis

September 2007

284 pages

ISBN:9781595938244

DOI:10.1145/1289816

General Chairs:
Soonhoi Ha
Seoul National University, Korea
,
Kiyoung Choi
Seoul National University, Korea
,
Program Chairs:
Nikil Dutt
UC Irvine, USA
,
Jürgen Teich
University of Erlangen-Nuremberg, Germany

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 September 2007

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ESWEEK07

Sponsor:

ESWEEK07: Third Embedded Systems Week

September 30 - October 3, 2007

Salzburg, Austria

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Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

View all

Pandith O(2024)SGXFault: An Efficient Page Fault Handling Mechanism for SGX EnclavesIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2023.326816921:3(1173-1178)Online publication date: May-2024
https://doi.org/10.1109/TDSC.2023.3268169
Khayatian MMehrabian MAndert EGrimsley RLiang KHu YMcCormack IJoe-Wong CAldrich JIannucci BShrivastava A(2022)Plan B: Design Methodology for Cyber-Physical Systems Robust to Timing FailuresACM Transactions on Cyber-Physical Systems10.1145/35164496:3(1-39)Online publication date: 7-Sep-2022
https://dl.acm.org/doi/10.1145/3516449
Roozkhosh SMancuso R(2020)The Potential of Programmable Logic in the Middle: Cache Bleaching2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS48715.2020.00006(296-309)Online publication date: Apr-2020
https://doi.org/10.1109/RTAS48715.2020.00006
Zhang TZheng WXiao YXu G(2020)A Dynamic Instruction Cache Locking Approach for Minimizing Worst Case Execution Time of a Single TaskIEEE Access10.1109/ACCESS.2020.30381708(208003-208015)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2020.3038170
Zhang TZheng WXiao Y(2020)WCET Aware Cache Locking and Task Scheduling in Single Core Embedded SystemsJournal of Physics: Conference Series10.1088/1742-6596/1684/1/0120871684(012087)Online publication date: 1-Dec-2020
https://doi.org/10.1088/1742-6596/1684/1/012087
Venkataramani VKulkarni AMitra TPeh LChen JShrivastava A(2019)SPECTRUM: a software defined predictable many-core architecture for LTE baseband processingProceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3316482.3326352(82-96)Online publication date: 23-Jun-2019
https://dl.acm.org/doi/10.1145/3316482.3326352
Venkanna MRao R(2018)Static Worst-Case Execution Time Optimization using DPSO for ASIP ArchitectureIngeniería Solidaria10.16925/.v14i0.223014:25(1-11)Online publication date: 1-May-2018
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Adegbija TGordon-Ross A(2018)PhLock: A Cache Energy Saving Technique Using Phase-Based Cache LockingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.275747726:1(110-121)Online publication date: Jan-2018
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Mitra TTeich JThiele L(2018)Time-Critical Systems Design: A SurveyIEEE Design & Test10.1109/MDAT.2018.279420435:2(8-26)Online publication date: Apr-2018
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Zheng WWu HNie C(2017)Integrating task scheduling and cache locking for multicore real-time embedded systemsACM SIGPLAN Notices10.1145/3140582.308103352:5(71-80)Online publication date: 21-Jun-2017
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