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Frame-aggregated concurrent matching switch

Published: 03 December 2007 Publication History
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  • Abstract

    Network operators need high-capacity router architectures that can offer scalability, provide throughput and performance guarantees, and maintain packet ordering. However, previous router architectures based on centralized crossbar-based architectures cannot scale to fast line rates and high port counts. Recently, a new scalable router architecture called the Concurrent Matching Switch (CMS)[5]was introduced that offers scalability by utilizing a fully distributed architecture based on two identical stages of fixed configuration meshes. It has been shown that fixed configuration meshes can be scaled to very fast line rates and highport counts via optical implementations.It has also been shown that the CMS architecture can achieve 100% through-put and packet ordering with only sequential hardware and O (1) amortized time complexity operations at each linecard. However, no delay performance guarantees have been shown for CMS.
    In this paper, we demonstrate a general delay performance guarantee for CMS.Based on this guarantee, we propose a novel frame-based CMS architecture that can achieve a performance guarantee of O (N log N)average packet delay, where N is the number of switch ports, while retaining scalability,throughput guarantees, packet ordering, and O (1) time complexity. This architecture improves upon the best previously-known average delay bound of O (N 2)given these switch properties. We further introduce several alternative frame-based CMS architectures.

    References

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    I. Keslassy, S. T. Chuang, K. Yu, D. Miller, M. Horowitz, O. Solgaard, and N. McKeown," Scaling Internet routers using optics," ACM SIGCOMM, Karlsruhe, Germany, 2003.
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    B. Lin, I. Keslassy, "A scalable switch for service guarantees," Proceedings of the 13th IEEE Symposium on High-Performance Interconnects, Aug 17-19, 2005.
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    B. Lin, I. Keslassy, "The concurrent matching switch architecture," IEEE INFOCOM, Barcelona, Spain, April 2006.
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    L. Tassiulas, "Linear complexity algorithms for maximum throughput in radio networks and input queued switches," IEEE INFOCOM, vol. 2,pp. 533--539, New York, 1998.
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    M. J. Neely, E. Modiano, Y.-S. Cheng, "Logarithmic delay for N x N packet switches under the crossbar constraint," IEEE Transactions on Networking, vol. 15, no. 3, pp. 657--668, June 2007.
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    J. Hopcroft, R. Karp, "An n 5/2 algorithm for maximum matchings in bipartite graphs,"SIAM J. Computing, pp. 225--231, December 1973.
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    Cited By

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    • (2012)A practical and scalable congestion control scheme for high-performance multi-stage buffered switches2012 IEEE 13th International Conference on High Performance Switching and Routing10.1109/HPSR.2012.6260826(44-51)Online publication date: Jun-2012
    • (2009)The interleaved matching switch architectureIEEE Transactions on Communications10.1109/TCOMM.2009.12.08038057:12(3732-3742)Online publication date: Dec-2009

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    Published In

    cover image ACM Conferences
    ANCS '07: Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems
    December 2007
    212 pages
    ISBN:9781595939456
    DOI:10.1145/1323548
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    New York, NY, United States

    Publication History

    Published: 03 December 2007

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    Author Tags

    1. 100% throughput
    2. concurrent matching switch
    3. frame scheduling
    4. load-balanced router
    5. packet switching

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    ANCS '07 Paper Acceptance Rate 20 of 70 submissions, 29%;
    Overall Acceptance Rate 88 of 314 submissions, 28%

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    • (2012)A practical and scalable congestion control scheme for high-performance multi-stage buffered switches2012 IEEE 13th International Conference on High Performance Switching and Routing10.1109/HPSR.2012.6260826(44-51)Online publication date: Jun-2012
    • (2009)The interleaved matching switch architectureIEEE Transactions on Communications10.1109/TCOMM.2009.12.08038057:12(3732-3742)Online publication date: Dec-2009

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