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Massive parallel LDPC decoding on GPU

Published: 20 February 2008 Publication History

Abstract

Low-Density Parity-Check (LDPC) codes are powerful error correcting codes (ECC). They have recently been adopted by several data communication standards such as DVB-S2 and WiMax. LDPCs are represented by bipartite graphs, also called Tanner graphs, and their decoding demands very intensive computation. For that reason, VLSI dedicated architectures have been investigated and developed over the last few years. This paper proposes a new approach for LDPC decoding on graphics processing units (GPUs). Efficient data structures and an new algorithm are proposed to represent the Tanner graph and to perform LDPC decoding according to the stream-based computing model. GPUs were programmed to efficiently implement the proposed algorithms by applying data-parallel intensive computing. Experimental results show that GPUs perform LDPC decoding nearly three orders of magnitude faster than modern CPUs. Moreover, they lead to the conclusion that GPUs with their tremendous processing power can be considered as a consistent alternative to state-of-the-art hardware LDPC decoders.

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  • (2017)High-throughput decoding of block turbo codes on graphics processing units2017 IEEE International Workshop on Signal Processing Systems (SiPS)10.1109/SiPS.2017.8109996(1-6)Online publication date: Oct-2017
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cover image ACM Conferences
PPoPP '08: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming
February 2008
308 pages
ISBN:9781595937957
DOI:10.1145/1345206
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 20 February 2008

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Author Tags

  1. computer unified device architecture
  2. cuda
  3. graphics processing unit
  4. ldpc
  5. low-density parity-check codes
  6. parallel processing

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Cited By

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  • (2019)High-Throughput Implementation of QC-LDPC on RaPro Prototyping PlatformCommunications, Signal Processing, and Systems10.1007/978-981-13-6264-4_13(108-115)Online publication date: 4-May-2019
  • (2018)FLAC Decoding Using GPU Acceleration2018 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Ubiquitous Computing & Communications, Big Data & Cloud Computing, Social Computing & Networking, Sustainable Computing & Communications (ISPA/IUCC/BDCloud/SocialCom/SustainCom)10.1109/BDCloud.2018.00035(155-162)Online publication date: Dec-2018
  • (2017)High-throughput decoding of block turbo codes on graphics processing units2017 IEEE International Workshop on Signal Processing Systems (SiPS)10.1109/SiPS.2017.8109996(1-6)Online publication date: Oct-2017
  • (2016)Implementation of decoders for symmetric low density parity check codes on parallel computation platforms using OpenCL2016 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)10.1109/CCECE.2016.7726832(1-6)Online publication date: May-2016
  • (2016)A Survey on Programmable LDPC DecodersIEEE Access10.1109/ACCESS.2016.25942654(6704-6718)Online publication date: 2016
  • (2016)Implementation of a Fully-Parallel Turbo Decoder on a General-Purpose Graphics Processing UnitIEEE Access10.1109/ACCESS.2016.25863094(5624-5639)Online publication date: 2016
  • (2015)Realizing Accelerated Cost-Effective Distributed RAIDHandbook on Data Centers10.1007/978-1-4939-2092-1_25(729-752)Online publication date: 17-Mar-2015
  • (2015)Efficient graphics processing unit based layered decoders for quasicyclic low-density parity-check codesConcurrency and Computation: Practice & Experience10.1002/cpe.319327:1(29-46)Online publication date: 1-Jan-2015
  • (2013)GPUs as Storage System AcceleratorsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2012.23924:8(1556-1566)Online publication date: 1-Aug-2013
  • (2012)A Multi-Directional Search technique for image annotation propagationJournal of Visual Communication and Image Representation10.1016/j.jvcir.2011.10.00423:1(237-244)Online publication date: 1-Jan-2012
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