research-article

Split hardware transactions: true nesting of transactions using best-effort hardware transactional memory

Authors:

Jan-Willem MaessenAuthors Info & Claims

PPoPP '08: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming

Pages 197 - 206

https://doi.org/10.1145/1345206.1345236

Published: 20 February 2008 Publication History

Abstract

Transactional Memory (TM) is on its way to becoming the programming API of choice for writing correct, concurrent, and scalable programs. Hardware TM (HTM) implementations are expected to be significantly faster than pure software TM (STM); however, full hardware support for true closed and open nested transactions is unlikely to be practical.

This paper presents a novel mechanism, the split hardware transaction (SpHT), that uses minimal software support to combine multiple segments of an atomic block, each executed using a separate hardware transaction, into one atomic operation. The idea of segmenting transactions can be used for many purposes, including nesting, local retry, orElse, and user-level thread scheduling; in this paper we focus on how it allows linear closed and open nesting of transactions. SpHT overcomes the limited expressive power of best-effort HTM while imposing overheads dramatically lower than STM and preserving useful guarantees such as strong atomicity provided by the underlying HTM.

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Cited By

Sheng YHassan ASpear M(2023)Separating Mechanism from Policy in STM2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT)10.1109/PACT58117.2023.00031(279-296)Online publication date: 21-Oct-2023
https://doi.org/10.1109/PACT58117.2023.00031
Soni MPal AMiguel J(2022)As-Is Approximate ComputingACM Transactions on Architecture and Code Optimization10.1145/355976120:1(1-26)Online publication date: 17-Nov-2022
https://dl.acm.org/doi/10.1145/3559761
Mohamedin MPalmieri RHassan ARavindran B(2017)Managing Resource Limitation of Best-Effort HTMIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2017.266841528:8(2299-2313)Online publication date: 1-Aug-2017
https://doi.org/10.1109/TPDS.2017.2668415
Show More Cited By

Index Terms

Split hardware transactions: true nesting of transactions using best-effort hardware transactional memory
1. Computing methodologies
  1. Parallel computing methodologies
    1. Parallel programming languages
2. Software and its engineering
  1. Software notations and tools
    1. General programming languages
      1. Language types
        Parallel programming languages

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cover image ACM Conferences

PPoPP '08: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming

February 2008

308 pages

ISBN:9781595937957

DOI:10.1145/1345206

General Chair:
Siddhartha Chatterjee
IBM Research USA
,
Program Chair:
Michael L. Scott
University of Rochester USA

Copyright © 2008 ACM.

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Published: 20 February 2008

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PPoPP08: ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming

February 20 - 23, 2008

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Overall Acceptance Rate 230 of 1,014 submissions, 23%

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Cited By

Sheng YHassan ASpear M(2023)Separating Mechanism from Policy in STM2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT)10.1109/PACT58117.2023.00031(279-296)Online publication date: 21-Oct-2023
https://doi.org/10.1109/PACT58117.2023.00031
Soni MPal AMiguel J(2022)As-Is Approximate ComputingACM Transactions on Architecture and Code Optimization10.1145/355976120:1(1-26)Online publication date: 17-Nov-2022
https://dl.acm.org/doi/10.1145/3559761
Mohamedin MPalmieri RHassan ARavindran B(2017)Managing Resource Limitation of Best-Effort HTMIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2017.266841528:8(2299-2313)Online publication date: 1-Aug-2017
https://doi.org/10.1109/TPDS.2017.2668415
Shahid AMurad MQadri MQadri NAhmed J(2016)Hardware Transactional MemoriesInnovative Research and Applications in Next-Generation High Performance Computing10.4018/978-1-5225-0287-6.ch003(47-65)Online publication date: 2016
https://doi.org/10.4018/978-1-5225-0287-6.ch003
Xiang LScott M(2015)Software partitioning of hardware transactionsACM SIGPLAN Notices10.1145/2858788.268850650:8(76-86)Online publication date: 24-Jan-2015
https://dl.acm.org/doi/10.1145/2858788.2688506
Liu YZhou TSpear MBlelloch GAgrawal K(2015)Transactional Acceleration of Concurrent Data StructuresProceedings of the 27th ACM symposium on Parallelism in Algorithms and Architectures10.1145/2755573.2755598(244-253)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2755573.2755598
Xiang LScott MCohen AGrove D(2015)Software partitioning of hardware transactionsProceedings of the 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/2688500.2688506(76-86)Online publication date: 24-Jan-2015
https://dl.acm.org/doi/10.1145/2688500.2688506
Su GHeisig S(2015)The Scalability of Disjoint Data Structures on a New Hardware Transactional Memory SystemInternational Journal of Parallel Programming10.1007/s10766-014-0322-943:6(1192-1217)Online publication date: 1-Dec-2015
https://dl.acm.org/doi/10.1007/s10766-014-0322-9
Harris TLarus JRajwar R(2010)Transactional Memory, 2nd editionSynthesis Lectures on Computer Architecture10.2200/S00272ED1V01Y201006CAC0115:1(1-263)Online publication date: 22-Dec-2010
https://doi.org/10.2200/S00272ED1V01Y201006CAC011
Sandes Ede Melo A(2010)CUDAlignACM SIGPLAN Notices10.1145/1837853.169347345:5(137-146)Online publication date: 9-Jan-2010
https://dl.acm.org/doi/10.1145/1837853.1693473
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