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VariaSim: simulating circuits and systems in the presence of process variability

Authors:

Bogdan F. Romanescu,

Michael E. Bauer,

Sule Ozev,

Daniel J. SorinAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 35, Issue 5

Pages 45 - 48

https://doi.org/10.1145/1360464.1360465

Published: 01 December 2007 Publication History

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Abstract

In this paper, we present VariaSim, the publicly available Static Statistical Timing Analysis (SSTA) Tool from Duke University. VariaSim enables researchers to analyze the impact of CMOS process variability on the behavior of circuits and systems.

References

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C. Amin et al. Statistical Static Timing Analysis: How Simple Can We Get? In Proceedings of the 42nd Design Automation Conference, pages 652--657, June 2005.

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L. Zhang et al. Correlation-Preserved Non-Gaussian Statistical Timing Analysis with Quadratic Timing Model. In Proceedings of the 42nd Design Automation Conference, pages 83--88, June 2005.

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Cited By

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Mittal S(2016)A Survey of Architectural Techniques for Managing Process VariationACM Computing Surveys10.1145/287116748:4(1-29)Online publication date: 9-Feb-2016
https://dl.acm.org/doi/10.1145/2871167
Romanescu BBauer MOzev SSorin DRamirez ABiliardi GGschwind M(2008)Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetchingProceedings of the 5th conference on Computing frontiers10.1145/1366230.1366257(129-138)Online publication date: 5-May-2008
https://dl.acm.org/doi/10.1145/1366230.1366257
Tehranipoor MAhmed N(2008)At-speed Test Challenges for Nanometer Technology DesignsNanometer Technology Designs High-Quality Delay Tests10.1007/978-0-387-75728-5_2(29-43)Online publication date: 2008
https://doi.org/10.1007/978-0-387-75728-5_2

Index Terms

VariaSim: simulating circuits and systems in the presence of process variability
1. Computing methodologies
  1. Modeling and simulation
    1. Simulation support systems
      1. Simulation environments
2. Hardware
  1. Integrated circuits
    1. Logic circuits

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cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 35, Issue 5

Special issue: ALPS '07---advanced low power systems

December 2007

73 pages

ISSN:0163-5964

DOI:10.1145/1360464

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Association for Computing Machinery

New York, NY, United States

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Published: 01 December 2007

Published in SIGARCH Volume 35, Issue 5

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Mittal S(2016)A Survey of Architectural Techniques for Managing Process VariationACM Computing Surveys10.1145/287116748:4(1-29)Online publication date: 9-Feb-2016
https://dl.acm.org/doi/10.1145/2871167
Romanescu BBauer MOzev SSorin DRamirez ABiliardi GGschwind M(2008)Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetchingProceedings of the 5th conference on Computing frontiers10.1145/1366230.1366257(129-138)Online publication date: 5-May-2008
https://dl.acm.org/doi/10.1145/1366230.1366257
Tehranipoor MAhmed N(2008)At-speed Test Challenges for Nanometer Technology DesignsNanometer Technology Designs High-Quality Delay Tests10.1007/978-0-387-75728-5_2(29-43)Online publication date: 2008
https://doi.org/10.1007/978-0-387-75728-5_2

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Optimized reversible binary-coded decimal adders

Hardware Designs for Decimal Floating-Point Addition and Related Operations

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Optimized reversible binary-coded decimal adders

Hardware Designs for Decimal Floating-Point Addition and Related Operations

Logic Networks of Carry-Save Adders

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