Fine-grain compensation method with consideration of trade-offs between computation and data transfer for power consumption
Pages 39 - 44
Abstract
Fine-grain parallelizing method with consideration of the number of data transfers for low power consumption is proposed. In the proposed method, power consumption by data transfers between processor elements in a multiprocessor is focused on, and the number of data transfers is reduced.
In this paper, a measure based on the relationship between variables in a given program is defined to evaluate the number of data transfers, firstly. And then a proposed compensation method by use of the evaluation of power consumption based on the measure is explained. Finally, the result of applying proposed compensation method implemented on COINS framework to several example programs is shown.
References
[1]
http://www.coinsproject.org. Coins project.
[2]
N. K. Jha. Low power system scheduling and synthesis. In ICCAD '01: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, pages 259--263, Piscataway, NJ, USA, 2001. IEEE Press.
[3]
H. Kasahara. Parallel Processing Technology. June 1991.
[4]
K. Lahiri, A. Raghunathan, and S. Dey. Fast system-level power profiling for battery-efficient system design. In CODES '02: Proceedings of the tenth international symposium on Hardware/software codesign, pages 157--162, New York, NY, USA, 2002. ACM Press.
[5]
M. T.-C. Lee, M. Fujita, V. Tiwari, and S. Malik. Power analysis and minimization techniques for embedded dsp software. IEEE Trans. Very Large Scale Integr. Syst., 5(1):123--135, 1997.
[6]
C.-G. Lyuh and T. Kim. Memory access scheduling and binding considering energy minimization in multi-bank memory systems. In DAC '04: Proceedings of the 41st annual conference on Design automation, pages 81--86, New York, NY, USA, 2004. ACM Press.
[7]
I. Matosevic, T. S. Abdelrahman, F. Karim, and A. Mellan. Power optimizations for the mlca using dynamic voltage scaling. In SCOPES '05: Proceedings of the 2005 workshop on Software and compilers for embedded systems, pages 109--123, New York, NY, USA, 2005. ACM Press.
[8]
O. Ozturk, G. Chen, M. Kandemir, and M. Karakoy. Cache miss clustering for banked memory systems. In ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, pages 244--250, New York, NY, USA, 2006. ACM Press.
[9]
A. Parikh, S. Kim, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. Instruction scheduling for low power. J. VLSI Signal Process. Syst., 37(1):129--149, 2004.
[10]
L. Shang and N. K. Jha. Hardware-software co-synthesis of low power real-time distributed embedded systems with dynamically reconfigurable fpgas. In ASP-DAC '02: Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, page 345, Washington, DC, USA, 2002. IEEE Computer Society.
[11]
Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. SH-3/SH-3E/SH3-DSPprogramming manual, 2000.
[12]
V. Tiwari, S. Malik, A. Wolfe, and M. T.-C. Lee. Instruction level power analysis and optimization of software. J. VLSI Signal Process. Syst., 13(2--3):223--238, 1996.
[13]
K. won Choi and A. Chatterjee. Efficient instruction-level optimization methodology for low-power embedded systems. In ISSS '01: Proceedings of the 14th international symposium on Systems synthesis, pages 147--152, New York, NY, USA, 2001. ACM Press.
[14]
D. Wu, B. M. Al-Hashimi, and P. Eles. Scheduling and mapping of conditional task graphs for the synthesis of low power embedded systems. In DATE '03: Proceedings of the conference on Design, Automation and Test in Europe, page 10090, Washington, DC, USA, 2003. IEEE Computer Society.
Index Terms
- Fine-grain compensation method with consideration of trade-offs between computation and data transfer for power consumption
Recommendations
The trade-off between power consumption and latency in computer networks
NETWORKING'11: Proceedings of the IFIP TC 6th international conference on NetworkingAs the power consumed by computer networks is nearly independent from the load, networks consume much more power than necessary when the load is low. We analyze the influence of disabling network components on power consumption and latency of data ...
Service center trade-offs between customer impatience and power consumption
We consider the problem of managing a service center where it is desirable to keep power consumption low. Customers defect (i.e. leave the system) if they have to wait too long before starting service. A block of servers is designated as 'reserve'. The ...
Dynamic management of power consumption
Power aware computingPower consumption of electronic devices has become a serious concern in the recent years. Power efficiency is necessary to lengthen the battery lifetime in the portable systems, as well as to reduce the operational costs and the environmental impact of ...
Comments
Information & Contributors
Information
Published In
Copyright © 2007 Authors.
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 01 December 2007
Published in SIGARCH Volume 35, Issue 5
Check for updates
Qualifiers
- Research-article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 65Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Reflects downloads up to 04 Oct 2024
Other Metrics
Citations
View Options
Get Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in