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A coarse-grained array based baseband processor for 100Mbps+ software defined radio

Published: 10 March 2008 Publication History

Abstract

The Software-Defined Radio (SDR) concept aims to enabling cost-effective multi-mode baseband solutions for wireless terminals. However, the growing complexity of new communication standards applying, e.g., multi-antenna transmission techniques, together with the reduced energy budget, is challenging SDR architectures. Coarse-Grained Array (CGA) processors are strong candidates to undertake both high performance and low power.
The design of a candidate hybrid CGA-SIMD processor for an SDR baseband platform is presented. The processor, designed in TSMC 90G process according to a dual-VT standard-cells flow, achieves a clock frequency of 400MHz in worst case conditions and consumes maximally 310mW active and 25mW leakage power (typical conditions) when delivering up to 25,6GOPS (16-bit). The mapping of a 20MHz 2x2 MIMO-OFDM transmit and receive baseband functionality is detailed as an application case study, achieving 100Mbps+ throughput with an average consumption of 220mW.

References

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J. Glossner, D. Iancu, L. Jin, E. Hokenek, M. Moudgill, "A software-defined communications baseband design," Communications Magazine, IEEE, Vol. 41, pp. 120--128, 2003.
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K. Van Berkel, H. F., P. Meuwissen, K. Moeren, M. Weiss, "Vector Processing as an Enabler for Software Defined Radio in Handsets for 3G+WLAN Onwards," SDR Forum Technical Conference, 2004, pp. 125--130.
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L. Yuan, L. Hyunseok, M. Woh, Y. Harel, S. Mahlke, T. Mudge, C. Chakrabarti, K. Flautner, "SODA: A Low-power Architecture For Software Radio," pp. 89--101, 2006.
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Cited By

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  • (2024)Coarse-grained reconfigurable architectures for radio baseband processing: A surveyJournal of Systems Architecture10.1016/j.sysarc.2024.103243(103243)Online publication date: Jul-2024
  • (2018)Coarse-Grained Reconfigurable Array ArchitecturesHandbook of Signal Processing Systems10.1007/978-3-319-91734-4_12(427-472)Online publication date: 14-Oct-2018
  • (2014)TomahawkACM Transactions on Embedded Computing Systems10.1145/251708713:3s(1-24)Online publication date: 28-Mar-2014
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cover image ACM Conferences
DATE '08: Proceedings of the conference on Design, automation and test in Europe
March 2008
1575 pages
ISBN:9783981080131
DOI:10.1145/1403375
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 10 March 2008

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DATE '08: Design, Automation and Test in Europe
March 10 - 14, 2008
Munich, Germany

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

View all
  • (2024)Coarse-grained reconfigurable architectures for radio baseband processing: A surveyJournal of Systems Architecture10.1016/j.sysarc.2024.103243(103243)Online publication date: Jul-2024
  • (2018)Coarse-Grained Reconfigurable Array ArchitecturesHandbook of Signal Processing Systems10.1007/978-3-319-91734-4_12(427-472)Online publication date: 14-Oct-2018
  • (2014)TomahawkACM Transactions on Embedded Computing Systems10.1145/251708713:3s(1-24)Online publication date: 28-Mar-2014
  • (2013)Coarse-Grained Reconfigurable Array ArchitecturesHandbook of Signal Processing Systems10.1007/978-1-4614-6859-2_18(553-592)Online publication date: 10-May-2013
  • (2012)A Variability-Aware Robust Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific ConstraintsACM Transactions on Embedded Computing Systems10.1145/2220336.222034111:2(1-28)Online publication date: 1-Jul-2012
  • (2012)Reducing the power of wireless terminals by adaptive baseband processingannals of telecommunications - annales des télécommunications10.1007/s12243-012-0289-867:3-4(161-170)Online publication date: 16-Feb-2012
  • (2011)State of the art baseband DSP platforms for Software Defined Radio: A surveyEURASIP Journal on Wireless Communications and Networking10.1186/1687-1499-2011-52011:1Online publication date: 6-Jun-2011
  • (2010)An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR ProcessorsJournal of Signal Processing Systems10.1007/s11265-009-0412-x61:2(157-179)Online publication date: 1-Nov-2010
  • (2010)Coarse-Grained Reconfigurable Array ArchitecturesHandbook of Signal Processing Systems10.1007/978-1-4419-6345-1_17(449-484)Online publication date: 16-Jul-2010
  • (2009)Algorithm-architecture co-design of soft-output ML MIMO detector for parallel application specific instruction set processorsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1875006(1608-1613)Online publication date: 20-Apr-2009
  • Show More Cited By

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